8(lge,lg1312-reflge,lg1312&/7LG Electronics, DTV SoC LG1312 Reference Boardcpuscpu@0=cpuarm,cortex-a53IM^cpu@1=cpuarm,cortex-a53IfpsciM^cpu@2=cpuarm,cortex-a53IfpsciM^cpu@3=cpuarm,cortex-a53IfpsciM^l2-cache0cache^psciarm,psci-0.2arm,pscimsmctinterrupt-controller@c0001000 arm,gic-4000I @ ` ^pmuarm,cortex-a53-pmu0timerarm,armv8-timer0   clk_bus fixed-clock =BUSCLK^soc simple-bus&ethernet@c1b00000 cdns,gem I   hclkpclkrmii&amba2 simple-bus&timer@fd100000 arm,sp804 I   apb_pclkwatchdog@fd200000arm,sp805arm,primecell I    apb_pclkserial@fe000000arm,pl011arm,primecell I   apb_pclkDokayserial@fe100000arm,pl011arm,primecell I   apb_pclk Ddisabledserial@fe200000arm,pl011arm,primecell I    apb_pclk Ddisabledspi@fe800000arm,pl022arm,primecell I   apb_pclkspi@fe900000arm,pl022arm,primecell I   apb_pclkdma@c1128000arm,pl330arm,primecell I   apb_pclkgpio@fd400000Karm,pl061arm,primecellW I@  apb_pclk Ddisabledgpio@fd410000Karm,pl061arm,primecellW IA  apb_pclk Ddisabledgpio@fd420000Karm,pl061arm,primecellW IB  apb_pclk Ddisabledgpio@fd430000Karm,pl061arm,primecellW IC  apb_pclkgpio@fd440000Karm,pl061arm,primecellW ID  apb_pclk Ddisabledgpio@fd450000Karm,pl061arm,primecellW IE  apb_pclk Ddisabledgpio@fd460000Karm,pl061arm,primecellW IF  apb_pclk Ddisabledgpio@fd470000Karm,pl061arm,primecellW IG  apb_pclk Ddisabledgpio@fd480000Karm,pl061arm,primecellW IH  apb_pclk Ddisabledgpio@fd490000Karm,pl061arm,primecellW II  apb_pclk Ddisabledgpio@fd4a0000Karm,pl061arm,primecellW IJ  apb_pclk Ddisabledgpio@fd4b0000Karm,pl061arm,primecellW IK  apb_pclkgpio@fd4c0000Karm,pl061arm,primecellW IL  apb_pclk Ddisabledgpio@fd4d0000Karm,pl061arm,primecellW IM  apb_pclk Ddisabledgpio@fd4e0000Karm,pl061arm,primecellW IN  apb_pclk Ddisabledgpio@fd4f0000Karm,pl061arm,primecellW IO  apb_pclk Ddisabledgpio@fd500000Karm,pl061arm,primecellW IP  apb_pclk Ddisabledgpio@fd510000Karm,pl061arm,primecellW IQ  apb_pclkaliasesg/amba/serial@fe000000o/amba/serial@fe100000w/amba/serial@fe200000memory=memory I chosenserial0:115200n8 #address-cells#size-cellscompatibleinterrupt-parentmodeldevice_typeregnext-level-cachephandleenable-methodcpu_suspendcpu_offcpu_on#interrupt-cellsinterrupt-controllerinterruptsinterrupt-affinity#clock-cellsclock-frequencyclock-output-namesrangesclocksclock-namesphy-modemac-address#interrupts-cellsstatus#gpio-cellsgpio-controllerserial0serial1serial2stdout-path