B98=L(=!,Rockchip RK3229 Evaluation board$2rockchip,rk3229-evbrockchip,rk3229aliases=/serial@11010000E/serial@11020000M/serial@11030000cpuscpu@f00Ucpu2arm,cortex-a7ael@cpu@f01Ucpu2arm,cortex-a7aelcpu@f02Ucpu2arm,cortex-a7aelcpu@f03Ucpu2arm,cortex-a7aelopp_table02operating-points-v2opp-408000000Q~@opp-600000000#Fopp-8160000000,B@opp-1008000000<opp-1200000000Gtxamba 2simple-buspdma@110f00002arm,pl330arm,primecella@  apb_pclkarm-pmu2arm,cortex-a7-pmu0LMNOtimer2arm,armv7-timer+0   On6oscillator 2fixed-clockOn6_xin24mri2s1@100b0000(2rockchip,rk3228-i2srockchip,rk3066-i2sa @  i2s_clki2s_hclkQtxrxdefault  disabledi2s0@100c0000(2rockchip,rk3228-i2srockchip,rk3066-i2sa @  i2s_clki2s_hclkP  txrx disabledi2s2@100e0000(2rockchip,rk3228-i2srockchip,rk3066-i2sa@  i2s_clki2s_hclkRtxrx disabledsyscon@110000002sysconsimple-mfdausb2-phy@7602rockchip,rk3228-usb2phya`  phyclk _usb480m_phy0rokay##otg-port$;<=otg-bvalidotg-idlinestateokay""host-port > linestateokay $$usb2-phy@8002rockchip,rk3228-usb2phya  phyclk _usb480m_phy1rokay%%otg-port D linestateokay &&host-port E linestateokay ''serial@110100002snps,dw-apb-uarta 7On6MU baudclkapb_pclkdefault   disabledserial@110200002snps,dw-apb-uarta 8On6NV baudclkapb_pclkdefault disabledserial@110300002snps,dw-apb-uarta 9On6OW baudclkapb_pclkdefaultokayi2c@110500002rockchip,rk3228-i2ca $ i2cLdefault disabledi2c@110600002rockchip,rk3228-i2ca % i2cMdefault disabledi2c@110700002rockchip,rk3228-i2ca & i2cNdefault disabledi2c@110800002rockchip,rk3228-i2ca ' i2cOdefault disabledwatchdog@110a0000 2snps,dw-wdta  (b disabledpwm@110b00002rockchip,rk3288-pwma ^ pwmdefault disabledpwm@110b00102rockchip,rk3288-pwma ^ pwmdefault disabledpwm@110b00202rockchip,rk3288-pwma ^ pwmdefault disabledpwm@110b00302rockchip,rk3288-pwma 0^ pwmdefault disabledtimer@110c0000,2rockchip,rk3228-timerrockchip,rk3288-timera  + a  timerpclkclock-controller@110e00002rockchip,rk3228-cruarHkb$#g0,eррxhррxhthermal-zonescpu-thermal4dJXtripscpu_alert0hpt\passivecpu_alert1h$t\passivecpu_crith_t \criticalcooling-mapsmap0 map1 tsadc@111500002rockchip,rk3228-tsadca :HX tsadcapb_pclkHeW tsadc-apbinitdefaultsleeps disableddwmmc@300200002rockchip,rk3288-dw-mshca0@ O<4`<4` Guy biuciuciu_drvciu_sample default  !eSreset disabledusb@3004000022rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2a0  otg"otg*<K@ Zd" iusb2-phyokayusb@30080000 2generic-ehcia0  #  usbhostutmid$iusbokayusb@300a0000 2generic-ohcia0   #  usbhostutmid$iusbokayusb@300c0000 2generic-ehcia0   %  usbhostutmid&iusbokayusb@300e0000 2generic-ohcia0  %  usbhostutmid&iusbokayusb@30100000 2generic-ehcia0 B %d'iusb  usbhostutmiokayusb@30120000 2generic-ohcia0 C %  usbhostutmid'iusbokayethernet@302000002rockchip,rk3228-gmaca0  macirq8~oM stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mace8 stmmacethokay}~ s(}input)rgmiidefault* + 'B@0interrupt-controller@32010000 2arm,gic-400 a22 2@ 2`   pinctrl2rockchip,rk3228-pinctrlgpio0@111100002rockchip,gpio-banka 3@#gpio1@111200002rockchip,gpio-banka 4A#gpio2@111300002rockchip,gpio-banka 5B#++gpio3@111400002rockchip,gpio-banka 6C#//pcfg-pull-up/..pcfg-pull-down<pcfg-pull-noneK,,pcfg-pull-none-drv-12maX --emmcemmc-clkg,emmc-cmdg,  emmc-bus8g,,,,,,,,!!gmacrgmii-pinsg, ,,---- - -,,,, ,,**rmii-pinsg, ,,-- -,,,,phy-pins g,,i2c0i2c0-xfer g,,i2c1i2c1-xfer g,,i2c2i2c2-xfer g,,i2c3i2c3-xfer g,,i2s1i2s1-busg, , , , ,,,,,  pwm0pwm0-ping,pwm1pwm1-ping,pwm2pwm2-ping ,pwm3pwm3-ping ,tsadcotp-gpiog,otp-outg,uart0uart0-xfer g,,  uart0-ctsg,  uart0-rtsg,  uart1uart1-xfer g , ,uart1-ctsg,uart1-rtsg ,uart2uart2-xfer g.,uart21-xfer g . ,uart2-ctsg,uart2-rtsg,usbhost-vbus-drvg,00memory@60000000Umemorya`@ext_gmac 2fixed-clockOsY@ _ext_gmacr((vcc-host-regulator2regulator-fixedu /default0 vcc_host  vcc-phy-regulator2regulator-fixeduvcc_phyw@w@)) #address-cells#size-cellsinterrupt-parentmodelcompatibleserial0serial1serial2device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclockslinux,phandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterrupts#dma-cellsclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsdmasdma-namespinctrl-namespinctrl-0statusinterrupt-names#phy-cellsphy-supplyreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempmax-frequencybus-widthdefault-sample-phasenum-slotsfifo-depthdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaphysphy-namesassigned-clock-parentsclock_in_outphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsenable-active-highregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvolt