Ð þíNí8I(ÙHÜ.,rockchip,px3-evbrockchip,px3rockchip,rk31887Rockchip PX3-EVBaliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000‚/serial@20064000Š/serial@20068000’/spi@20070000—/spi@20074000amba ,simple-busœdma-controller@20018000,arm,pl330arm,primecell£ €@§²½ØÀ ßapb_pclkë+ñ+dma-controller@2001c000,arm,pl330arm,primecell£ À@§²½ØÀ ßapb_pclk ùdisableddma-controller@20078000,arm,pl330arm,primecell£ €@§²½ØÁ ßapb_pclkëñoscillator ,fixed-clockn6xin24ml2-cache-controller@10138000,arm,pl310-cache£€0>ë(ñ(scu@1013c000,arm,cortex-a9-scu£Àglobal-timer@1013c200,arm,cortex-a9-global-timer£  § Ø ùdisabledlocal-timer@1013c600,arm,cortex-a9-twd-timer£Æ  § Øinterrupt-controller@1013d000,arm,cortex-a9-gicJ_£ÐÁëñserial@10124000&,rockchip,rk3188-uartsnps,dw-apb-uart£@ §"pzßbaudclkapb_pclkØ@Lùokay‡default•serial@10126000&,rockchip,rk3188-uartsnps,dw-apb-uart£` §#pzßbaudclkapb_pclkØAMùokay‡default•usb@10180000,rockchip,rk3066-usbsnps,dwc2£ §ØÃßotgŸotg§¹È€€@@ × Üusb2-phyùokayusb@101c0000 ,snps,dwc2£ §ØÉßotgŸhost× Üusb2-phyùokayethernet@10204000,rockchip,rk3188-emac£ @< §æØÄD ßhclkmacrefódýrmii ùdisableddwmmc@10214000,rockchip,rk2928-dw-mshc£!@ §ØÀHßbiuciu rx-tx Q'resetùokay3‡default• = ISevdwmmc@10218000,rockchip,rk2928-dw-mshc£!€ §ØÁIßbiuciu rx-tx R'reset ùdisableddwmmc@1021c000,rockchip,rk2928-dw-mshc£!À §ØÂJßbiuciu rx-tx S'resetùokayISv3‡default •pmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd£ @ë-ñ-reboot-mode,syscon-reboot-mode@–RBâRBðRBà ÀRBÃgrf@20008000,syscon£ €ëñi2c@2002d000,rockchip,rk3188-i2c£ Ð §(æßi2cØPùokay‡default•accelerometer@18 ,bosch,bma250£§i2c@2002f000,rockchip,rk3188-i2c£ ð §)æØQßi2cùokay‡default•€pmic@1c,rockchip,rk818£§ Ìíxin32krk808-clkout2û+7COregulatorsDCDC_REG1[o q°™™p±vdd_armë)ñ)regulator-state-memÀDCDC_REG2[o øP™Ð±vdd_gpuregulator-state-memÙñB@DCDC_REG3[o±vcc_ddrregulator-state-memÙDCDC_REG4[o2Z ™2Z ±vcc_ioëñregulator-state-memÙñ2Z LDO_REG12Z ™2Z ±vcc_cifLDO_REG2[o2Z ™2Z  ±vcc_jetta33LDO_REG3[oB@™B@±vdd_10regulator-state-memÙñB@LDO_REG4w@™w@±lvds_12LDO_REG5w@™2Z ±lvds_25LDO_REG6B@™B@±cif_18LDO_REG7w@™2Z ±vcc_sdë ñ regulator-state-memÙñ2Z LDO_REG8w@™2Z ±wl_18SWITCH_REG1±lcd_33pwm@20030000,rockchip,rk2928-pwm£  ØF ùdisabled‡default•pwm@20030010,rockchip,rk2928-pwm£  ØFùokay‡default•watchdog@2004c000 ,rockchip,rk3188-wdtsnps,dw-wdt£ ÀØK §3ùokaypwm@20050020,rockchip,rk2928-pwm£   ØGùokay‡default•pwm@20050030,rockchip,rk2928-pwm£ 0 ØGùokay‡default•i2c@20056000,rockchip,rk3188-i2c£ ` §*æØRßi2c ùdisabled‡default•touchscreen@40,silead,gsl1680£@§ $ 7Ji2c@2005a000,rockchip,rk3188-i2c£   §+æØSßi2c ùdisabled‡default•i2c@2005e000,rockchip,rk3188-i2c£ à §4æØTßi2c ùdisabled‡default•serial@20064000&,rockchip,rk3188-uartsnps,dw-apb-uart£ @ §$pzßbaudclkapb_pclkØBNùokay‡default•serial@20068000&,rockchip,rk3188-uartsnps,dw-apb-uart£ € §%pzßbaudclkapb_pclkØCOùokay‡default•saradc@2006c000,rockchip,saradc£ À §]ØGJßsaradcapb_pclk W 'saradc-apb ùdisabledspi@20070000(,rockchip,rk3188-spirockchip,rk3066-spiØEHßspiclkapb_pclk §&£    txrx ùdisabled‡default• !"#spi@20074000(,rockchip,rk3188-spirockchip,rk3066-spiØFIßspiclkapb_pclk §'£ @   txrx ùdisabled‡default•$%&'cpusorockchip,rk3066-smpcpu@0}cpu,arm,cortex-a9‰(£@š‰@™p›@ÐO€Œ0a€g8 s€à˜ 'À~ð°ÀHÂÀ Yø«œ@ع)cpu@1}cpu,arm,cortex-a9‰(£cpu@2}cpu,arm,cortex-a9‰(£cpu@3}cpu,arm,cortex-a9‰(£sram@10080000 ,mmio-sram£€ œ€smp-sram@0,rockchip,rk3066-smp-sram£Ptimer@2000e000,,rockchip,rk3188-timerrockchip,rk3288-timer£ à  §.ØWE ßtimerpclktimer@200380a0,,rockchip,rk3188-timerrockchip,rk3288-timer£ €   §@ØZB ßtimerpclki2s@1011a000(,rockchip,rk3188-i2srockchip,rk3066-i2s£   § ‡default•*++ txrxßi2s_hclki2s_clkØÆKÅà ùdisabledsound@1011e000,,rockchip,rk3188-spdifrockchip,rk3066-spdif£à ú ßhclkmclkØÅN+ tx § ‡default•, ùdisabledclock-controller@20000000,rockchip,rk3188-cru£ æ ëñefuse@20010000,rockchip,rk3188-efuse£ @Ø[ ßpclk_efusecpu_leakage@17£phy0,rockchip,rk3188-usb-phyrockchip,rk3288-usb-phyæùokayusb-phy@10c£ ØQßphyclkëñusb-phy@11c£ØRßphyclkëñpinctrl,rockchip,rk3188-pinctrlæ#-œgpio0@2000a000,rockchip,rk3188-gpio-bank0£   §6ØU0@J_ëñgpio1@2003c000,rockchip,gpio-bank£ À §7ØV0@J_ëñgpio2@2003e000,rockchip,gpio-bank£ à §8ØW0@J_gpio3@20080000,rockchip,gpio-bank£  §9ØX0@J_pcfg_pull_upLë/ñ/pcfg_pull_downYpcfg_pull_nonehë.ñ.emmcemmc-clku.ëñemmc-cmdu/ëñemmc-rstu.ëñemacemac-xfer€u........emac-mdio u..i2c0i2c0-xfer u..ëñi2c1i2c1-xfer u..ëñi2c2i2c2-xfer u..ëñi2c3i2c3-xfer u..ëñi2c4i2c4-xfer u..ëñpwm0pwm0-outu.ëñpwm1pwm1-outu.ëñpwm2pwm2-outu.ëñpwm3pwm3-outu.ëñspi0spi0-clku/ë ñ spi0-cs0u/ë#ñ#spi0-txu/ë!ñ!spi0-rxu/ë"ñ"spi0-cs1u/spi1spi1-clku/ë$ñ$spi1-cs0u/ë'ñ'spi1-rxu/ë&ñ&spi1-txu/ë%ñ%spi1-cs1u/uart0uart0-xfer u/.ëñuart0-ctsu.uart0-rtsu.uart1uart1-xfer u/.ëñuart1-ctsu.uart1-rtsu.uart2uart2-xfer u/ .ëñuart3uart3-xfer u / .ëñuart3-ctsu .uart3-rtsu .sd0sd0-clku.ë ñ sd0-cmdu.ë ñ sd0-cdu.ë ñ sd0-wpu .sd0-pwru.sd0-bus-width1u.sd0-bus-width4@u....ë ñ sd1sd1-clku.sd1-cmdu.sd1-cdu.sd1-wpu.sd1-bus-width1u.sd1-bus-width4@u....i2s0i2s0-bus`u......ë*ñ*spdifspdif-txu.ë,ñ,pcfg-output-lowƒusbhost-vbus-drvu.otg-vbus-drvu.chosenŽserial2:115200n8memory@60000000£`€}memorygpio-keys ,gpio-keysšpower ¥t°GPIO Key Power¶íÇdvsys-regulator,regulator-fixed±vsysLK@™LK@oëñ #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-nameslinux,phandlestatusclock-frequency#clock-cellsclock-output-namescache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modedmasdma-namesfifo-depthresetsreset-namesnum-slotsvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpnon-removableoffsetmode-normalmode-recoverymode-bootloadermode-loaderrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspower-gpiostouchscreen-size-xtouchscreen-size-ysilead,max-fingers#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu0-supplyrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cells#phy-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disablerockchip,pinsoutput-lowstdout-pathautorepeatlinux,codelabellinux,input-typedebounce-interval