28\($,TRONFY MXQ S8052tronfy,mxqamlogic,meson8bchosenaliases=/soc/aobus@c8100000/serial@4c0memoryEmemoryQ@@l2-cache-controller@c42000002arm,pl310-cacheQ Uc o   interrupt-controller@c43010002arm,cortex-a9-gicQ00soc 2simple-buscbus@c1100000 2simple-busQ   rng@8100&2amlogic,meson8b-rngamlogic,meson-rngQcoreserial@84c02amlogic,meson-uartQ  disabled serial@84dc2amlogic,meson-uartQ K disabled i2c@85002amlogic,meson6-i2cQ   disabledadc@8680,2amlogic,meson8b-saradcamlogic,meson-saradcQ4 I disabledEclkincoresanaserial@87002amlogic,meson-uartQ ] disabled i2c@87c02amlogic,meson6-i2cQ   disabledphy@880032amlogic,meson8b-usb2-phyamlogic,meson-mx-usb2-phy Q  disabled72usb_generalusb"phy@882032amlogic,meson8b-usb2-phyamlogic,meson-mx-usb2-phy Q  disabled73usb_generalusb"spi@8c802amlogic,meson6-spifcQ disabledwatchdog@99002amlogic,meson8b-wdtQ timer@99402amlogic,meson6-timerQ@ clock-controller@40002amlogic,meson8b-clkcQ@`reset-controller@44042amlogic,meson8b-resetQD ,pwm@85502amlogic,meson8b-pwmQP9 disabledpwm@86502amlogic,meson8b-pwmQP9 disabledpwm@86c02amlogic,meson8b-pwmQ9 disabledpinctrl@98802amlogic,meson8b-cbus-pinctrlQbanks@80b0 Q( 08Dmuxpullpull-enablegpioN^jaobus@c8100000 2simple-busQ ir-receiver@4802amlogic,meson6-irQ   disabledserial@4c02amlogic,meson-uartQ Zokay vdefaulti2c@5002amlogic,meson6-i2cQ  \ disabledpinctrl@842amlogic,meson8b-aobus-pinctrlQ ao-bank@14Q,$DmuxpullgpioN^juart_ao_amuxuart_tx_ao_auart_rx_ao_auart_aousb@c90400002amlogic,meson8b-usbsnps,dwc2Q  usb2-phyhost disabledAotgusb@c90c00002amlogic,meson8b-usbsnps,dwc2Q   usb2-phyhost disabled@otgethernet@c9410000 2amlogic,meson6-dwmacsnps,dwmacQA macirq disabled$ stmmacethcpuscpu@200Ecpu2arm,cortex-a5 Qcpu@201Ecpu2arm,cortex-a5 Qcpu@202Ecpu2arm,cortex-a5 Qcpu@203Ecpu2arm,cortex-a5 Qscu@c43000002arm,cortex-a5-scuQ0 #address-cells#size-cellsinterrupt-parentmodelcompatibleserial0device_typeregcache-unifiedcache-levelarm,data-latencyarm,tag-latencyarm,filter-rangeslinux,phandleinterrupt-controller#interrupt-cellsclocksclock-namesinterruptsstatus#io-channel-cells#phy-cellsresets#clock-cells#reset-cells#pwm-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinctrl-0pinctrl-namesgroupsfunctionphysphy-namesdr_modeinterrupt-namesnext-level-cache