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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1serial0serial1serial2ethernet0ethernet1device_typereginterruptsti,hwmodsranges#clock-cellsclockslinux,phandleti,bit-shiftti,max-divti,dividers#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsreg-namesclock-names#phy-cellssysconclock-frequencyclock-indicesclock-output-names#dma-cellsti,gpio-always-ongpio-controller#gpio-cellsinterrupt-controller#interrupt-cellsdmasdma-namesgpmc,num-csgpmc,num-waitpinspinctrl-namespinctrl-0linux,mtd-namerb-gpiosti,nand-ecc-optti,elm-idnand-bus-widthgpmc,device-widthgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,clk-activation-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabel#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rx#hwlock-cellsbus_freqti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizephy-handleti,spi-num-csspi-max-frequencyvmmc-supplycd-gpioswp-gpiosti,timer-alwonti,timer-pwminterrupt-namesdr_modeinterface-typephysphy-namesmentor,multipointmentor,num-epsmentor,ram-bitsmentor,power#dma-channels#dma-requestsregulator-nameregulator-min-microvoltregulator-max-microvolt