Š žķ0Ż8-((µ,šxlnx,zynq-zc702xlnx,zynq-7000&Zynq ZC702 Development Boardchosen ,earlycon5serial0:115200n8aliasesA/amba/ethernet@e000b000K/amba/i2c@e0004000P/amba/serial@e0001000memoryXmemoryd@cpuscpu@0arm,cortex-a9Xcpudhoč}‰ ,+B@B@cpu@1arm,cortex-a9Xcpudhpmuarm,cortex-a9-pmuš„dų‰ų‰0fixedregulator@0regulator-fixed¶VCCPINTÅB@ŻB@õ!amba simple-bus„)adc@f8007100xlnx,zynq-xadc-1.00.adųq  š„h can@e0008000xlnx,zynq-can-1.00okayh$ 7can_clkpclkdą€ š„C@Q@_defaultmcan@e0009000xlnx,zynq-can-1.0 0disabledh% 7can_clkpclkdą š3„C@Q@gpio@e000a000xlnx,zynq-gpio-1.0wh*ƒ“Ø„ šdą _defaultm!i2c@e0004000cdns,i2c-r1p100okayh&„ šdą@¹€_defaultmi2cswitch@74 nxp,pca9548dti2c@0dclock-generator@5dÉ silabs,si570Ö2d]ģ P/¹Łī i2c@2deeprom@54 at,24c08dTi2c@3dgpio@21 ti,tca6416d!ƒwi2c@4drtc@51 nxp,pcf8563dQi2c@7dhwmon@52 ti,ucd9248d4hwmon@53 ti,ucd9248d5hwmon@54 ti,ucd9248d6i2c@e0005000cdns,i2c-r1p10 0disabledh'„ š0dąPinterrupt-controller@f8f01000arm,cortex-a9-gicØ“dųšųš!cache-controller@f8f02000arm,pl310-cachedųš  š ł  (memory-controller@f8006000xlnx,zynq-ddrc-a05dų`serial@e0000000xlnx,xuartpscdns,uart-r1p8 0disabledh(7uart_clkpclkdą šserial@e0001000xlnx,xuartpscdns,uart-r1p80okayh)7uart_clkpclkdą š2_defaultmspi@e0006000xlnx,zynq-spi-r1p6dą` 0disabled„ šh" 7ref_clkpclkspi@e0007000xlnx,zynq-spi-r1p6dąp 0disabled„ š1h# 7ref_clkpclkethernet@e000b000cdns,zynq-gemcdns,gemdą°0okay šh 7pclkhclktx_clk 4rgmii-id=_defaultm ethernet-phy@7d!ethernet@e000c000cdns,zynq-gemcdns,gemdąĄ 0disabled š-h7pclkhclktx_clksdhci@e0100000arasan,sdhci-8.9a0okay7clk_xinclk_ahbh „ šdą_defaultm sdhci@e0101000arasan,sdhci-8.9a 0disabled7clk_xinclk_ahbh!„ š/dąslcr@f8000000!xlnx,zynq-slcrsysconsimple-mfddų) ! clkc@100Éxlnx,ps7-clkcHjTarmpllddrplliopllcpu_6or4xcpu_3or2xcpu_2xcpu_1xddr2xddr3xdcilqspismcpcapgem0gem1fclk0fclk1fclk2fclk3can0can1sdio0sdio1uart0uart1spi0spi1dmausb0_aperusb1_apergem0_apergem1_apersdio0_apersdio1_aperspi0_aperspi1_apercan0_apercan1_aperi2c0_aperi2c1_aperuart0_aperuart1_apergpio_aperlqspi_apersmc_aperswdtdbg_trcdbg_apbdgü U!rstc@200xlnx,zynq-resetdHx… pinctrl@700xlnx,pinctrl-zynqd… can0-default!muxŒcan0 •can0_9_grpconf •can0_9_grpœ¦conf-rx²MIO46·conf-tx²MIO47Ėgem0-default ! mux Œethernet0•ethernet0_0_grpconf•ethernet0_0_grpœ¦conf-rx$²MIO22MIO23MIO24MIO25MIO26MIO27·Ųconf-tx$²MIO16MIO17MIO18MIO19MIO20MIO21Ėźmux-mdioŒmdio0 •mdio0_0_grpconf-mdio •mdio0_0_grpœ¦Ėgpio0-default!muxŒgpio0e•gpio0_7_grpgpio0_8_grpgpio0_9_grpgpio0_10_grpgpio0_11_grpgpio0_12_grpgpio0_13_grpgpio0_14_grpconfe•gpio0_7_grpgpio0_8_grpgpio0_9_grpgpio0_10_grpgpio0_11_grpgpio0_12_grpgpio0_13_grpgpio0_14_grpœ¦conf-pull-up#²MIO9MIO10MIO11MIO12MIO13MIO14ūconf-pull-none ²MIO7MIO8Ėi2c0-default!mux •i2c0_10_grpŒi2c0conf •i2c0_10_grpūœ¦sdhci0-default ! mux •sdio0_2_grpŒsdio0conf •sdio0_2_grpœ¦Ėmux-cd •gpio0_0_grp Œsdio0_cdconf-cd •gpio0_0_grp·ūœ¦mux-wp •gpio0_15_grp Œsdio0_wpconf-wp •gpio0_15_grp·ūœ¦uart1-default!mux •uart1_10_grpŒuart1conf •uart1_10_grpœ¦conf-rx²MIO49·conf-tx²MIO48Ėusb0-default ! mux •usb0_0_grpŒusb0conf •usb0_0_grpœ¦conf-rx²MIO29MIO31MIO36·conf-tx6²MIO28MIO30MIO32MIO33MIO34MIO35MIO37MIO38MIO39Ėdmac@f8003000arm,pl330arm,primecelldų0„.abortdma0dma1dma2dma3dma4dma5dma6dma7lš ()*+#1h 7apb_pclkdevcfg@f8007000xlnx,zynq-devcfg-1.0dųp„ šh 7ref_clk… timer@f8f00200arm,cortex-a9-global-timerdųš  š „htimer@f8001000„$š    cdns,ttchdųtimer@f8002000„$š%&' cdns,ttchdų timer@f8f00600„ š arm,cortex-a9-twd-timerdųš husb@e0002000"xlnx,zynq-usb-2.20achipidea,usb20okayh„ šdą ?ulpiHhostP _defaultm usb@e0003000"xlnx,zynq-usb-2.20achipidea,usb2 0disabledh„ š,dą0?ulpiwatchdog@f8005000h-cdns,wdt-r1p2„ š dųPX sram@fffc0000 mmio-sramd’ügpio-keys gpio-keysdsw14osw14 u {l†dsw13osw13 u{g†dleds gpio-ledsds23ods23 u  ”heartbeatphy0usb-nop-xceivŖ !  #address-cells#size-cellscompatiblemodelbootargsstdout-pathethernet0i2c0serial0device_typeregclocksclock-latencycpu0-supplyoperating-pointsinterruptsinterrupt-parentregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onlinux,phandlerangesstatusclock-namestx-fifo-depthrx-fifo-depthpinctrl-namespinctrl-0#gpio-cellsgpio-controllerinterrupt-controller#interrupt-cellsclock-frequency#clock-cellstemperature-stabilityfactory-foutarm,data-latencyarm,tag-latencycache-unifiedcache-levelphy-modephy-handlefclk-enableclock-output-namesps-clk-frequency#reset-cellssysconfunctiongroupsslew-rateio-standardpinsbias-high-impedancebias-disablelow-power-disablelow-power-enablebias-pull-upinterrupt-names#dma-cells#dma-channels#dma-requestsphy_typedr_modeusb-phytimeout-secautorepeatlabelgpioslinux,codewakeup-sourcelinux,default-trigger#phy-cells