c8L( google,veyron-speedy-rev9google,veyron-speedy-rev8google,veyron-speedy-rev7google,veyron-speedy-rev6google,veyron-speedy-rev5google,veyron-speedy-rev4google,veyron-speedy-rev3google,veyron-speedy-rev2google,veyron-speedygoogle,veyronrockchip,rk3288&7Google Speedychosenaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/spi@ff110000/ec@0/i2c-tunnelmemorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12h w@\@p@ @@OOa sB@ ~ ' 9 K 0 *@8?KQcpu@501cpuarm,cortex-a12KQcpu@502cpuarm,cortex-a12KQcpu@503cpuarm,cortex-a12KQamba simple-busYdma-controller@ff250000arm,pl330arm,primecell%@`k8 apb_pclkKQdma-controller@ff600000arm,pl330arm,primecell`@`k8 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@`k8 apb_pclkKQQQreserved-memoryYdma-unusable@fe000000oscillator fixed-clockn6xin24mK Q timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 8 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 8Drvbiuciuciu-driveciu-sample  @okay-> P YZw defaultdwmmc@ff0d0000rockchip,rk3288-dw-mshcр 8Eswbiuciuciu-driveciu-sample ! @okay- wdefault dwmmc@ff0e0000rockchip,rk3288-dw-mshcр 8Ftxbiuciuciu-driveciu-sample "@ disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 8Guybiuciuciu-driveciu-sample #@okayY. wdefault saradc@ff100000rockchip,saradc $=8I[saradcapb_pclkW Osaradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi8ARspiclkapb_pclk[  `txrx ,default !"okayec@0google,cros-ec-spij& default#-i2c-tunnelgoogle,cros-ec-i2c-tunnelsbs-battery@bsbs,sbs-battery keyboard-controllergoogle,cros-ec-keyb @};0DY1 d>"A#( C  \=@V B |)<?   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi8BSspiclkapb_pclk[ `txrx -default$%&' disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi8CTspiclkapb_pclk[`txrx .default()*+okay flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c8Mdefault,okay12Idtpm@20infineon,slb9645tt `i2c@ff150000rockchip,rk3288-i2c ?i2c8Odefault- disabledi2c@ff160000rockchip,rk3288-i2c @i2c8Pdefault.okay12I,ts3a227e@3b ti,ts3a227e;&/default0xKQtrackpad@15elan,ekth3000& default12i2c@ff170000rockchip,rk3288-i2c Ai2c8Qdefault3okay1,IKcQcserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 78MUbaudclkapb_pclkdefault 456okayMlserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 88NVbaudclkapb_pclkdefault7okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 98OWbaudclkapb_pclkdefault8okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :8PXbaudclkapb_pclkdefault9 disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;8QYbaudclkapb_pclkdefault: disabledthermal-zonesreserve_thermal;cpu_thermald;tripscpu_alert0 passiveK<Q<cpu_alert1 ppassiveK=Q=cpu_crit _ criticalcooling-mapsmap0#< (map1#= (gpu_thermald;tripsgpu_alert0 ppassiveK>Q>gpu_crit _ criticalcooling-mapsmap0#> (tsadc@ff280000rockchip,rk3288-tsadc( %8HZtsadcapb_pclk Otsadc-apbinitdefaultsleep?7@A?KasokayxK;Q;ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irqA88fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB Ostmmaceth disabledusb@ff500000 generic-ehciP 8usbhostBusbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 8otghostC usb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 8otghost@@ $D usb2-phyokayz.Dusb@ff5c0000 generic-ehci\ 8usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c8LdefaultEokay12Idpmic@1brockchip,rk808xin32kwifibt_32kin&/defaultFEfr~G2GGKuQuregulatorsDCDC_REG1vdd_arm / qG _qKQregulator-state-memtDCDC_REG2vdd_gpu / 5G_qregulator-state-memB@DCDC_REG3 vcc135_ddr regulator-state-memDCDC_REG4vcc_18 /w@Gw@KQregulator-state-memw@LDO_REG1 vcc33_io /2ZG2ZK2Q2regulator-state-mem2ZLDO_REG3vdd_10 /B@GB@regulator-state-memB@LDO_REG7vdd10_lcd_pwren_h /&%G&%regulator-state-memtSWITCH_REG1 vcc33_lcd KOQOregulator-state-memtLDO_REG6 vcc18_codec /w@Gw@KPQPregulator-state-memtLDO_REG4 vccio_sd/w@G2ZKQregulator-state-memtLDO_REG5 vcc33_sd/2ZG2ZK Q regulator-state-memtLDO_REG8 vcc33_ccd /2ZG2Zregulator-state-mem2Zi2c@ff660000rockchip,rk3288-i2cf =i2c8NdefaultHokay12I max98090@10maxim,max98090&Imclk8qdefaultJKQpwm@ff680000rockchip,rk3288-pwmhdefaultK8^pwmokayKQpwm@ff680010rockchip,rk3288-pwmhdefaultL8^pwmokaypwm@ff680020rockchip,rk3288-pwmh defaultM8^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0defaultN8^pwm disabledbus_intmem@ff700000 mmio-sramp Ypsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsKQpower-controller!rockchip,rk3288-power-controllerh. KTQTpd_vio@9 8chgfdehilkjpd_hevc@11 8oppd_video@12 8pd_gpu@13 8syscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvAHjk$#gׄeрxhрxhKQsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwKAQAedp-phyrockchip,rk3288-dp-phy8h24mokayK_Q_io-domains"rockchip,rk3288-io-voltage-domainokay2 2+29OEQP^watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt8p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdifl hclkmclk8T[Q`tx 6defaultRA disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5[QQ`txrxi2s_hclki2s_clk8RdefaultS}okayKQcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 8}aclkhclksclkapb_pclk Ocrypto-rstokayvop@ff930000rockchip,rk3288-vop 8aclk_vopdclk_vophclk_vopT def OaxiahbdclkUokayportK Q endpoint@0VKdQdendpoint@1WK`Q`endpoint@2XK]Q]iommu@ff930300rockchip,iommu  vopb_mmuT okayKUQUvop@ff940000rockchip,rk3288-vop 8aclk_vopdclk_vophclk_vopT  OaxiahbdclkYokayportK Q endpoint@0ZKeQeendpoint@1[KaQaendpoint@2\K^Q^iommu@ff940300rockchip,iommu  vopl_mmuT okayKYQYmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 8~d refpclkT A disabledportsportendpoint@0]KXQXendpoint@1^K\Q\dp@ff970000rockchip,rk3288-dp@ b8icdppclk_dpoOdpAokayportsport@0endpoint@0`KWQWendpoint@1aK[Q[port@1endpointbKQhdmi@ff980000rockchip,rk3288-dw-hdmiA g8hm iahbisfrT okaycportsportendpoint@0dKVQVendpoint@1eKZQZinterrupt-controller@ffc01000 arm,gic-400   @ `   KQefuse@ffb40000rockchip,rockchip-efuse 8q pclk_efusecpu_leakage@17phyrockchip,rk3288-usb-phyAokayusb-phy@320 8]phyclkKDQDusb-phy@33448^phyclkKBQBusb-phy@348H8_phyclkKCQCpinctrlrockchip,rk3288-pinctrlAYdefaultsleepfg7fhgpio0@ff750000rockchip,gpio-banku Q8@  0 K/Q/gpio1@ff780000rockchip,gpio-bankx R8A  0 gpio2@ff790000rockchip,gpio-banky S8B  0 KtQtgpio3@ff7a0000rockchip,gpio-bankz T8C  0 gpio4@ff7b0000rockchip,gpio-bank{ U8D  0 KxQxgpio5@ff7c0000rockchip,gpio-bank| V8E  0 K{Q{gpio6@ff7d0000rockchip,gpio-bank} W8F  0 KIQIgpio7@ff7e0000rockchip,gpio-bank~ X8G  0 K Q gpio8@ff7f0000rockchip,gpio-bank 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<oKhQhtrackpadtrackpad-int <jK1Q1usb-hosthost1-pwr-en < iKQusbotg-pwren-h < iKQbuck-5vdrv-5v <iKzQzlcdlcd-en <iKQavdd-1v8-disp-en < iKQgpio-keys gpio-keysdefaultpqpower Power S/ t dlid Lid S/   gpio-restart gpio-restart S/ defaultr emmc-pwrseqmmc-pwrseq-emmcsdefault t KQsdio-pwrseqmmc-pwrseq-simple8u ext_clockdefaultvw xKQvcc-5vregulator-fixedvcc_5v /LK@GLK@ y  defaultzKGQGvcc33-sysregulator-fixed vcc33_sys /2ZG2Z yKQvcc50-hdmiregulator-fixed vcc50_hdmi  G  {default|sound!rockchip,rockchip-audio-max98090default}~ VEYRON-I2S  , AI WI  nbacklightpwm-backlight   !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~   default B@ ' KQgpio-charger gpio-charger mains S/defaultpanelinnolux,n116bgesimple-panelokay  portsportendpointKbQbvccsysregulator-fixedvccsys KyQyvcc5-host1-regulatorregulator-fixed  / default vcc5_host1 vcc5v-otg-regulatorregulator-fixed  / default vcc5_host2 panel-regulatorregulator-fixed  defaultpanel_regulator  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#address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2i2c20device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsclock-freq-min-maxfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasenum-slotssd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemmc-hs200-1_8v#io-channel-cellsreset-namesdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-widthassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphysphy-namesneeds-reset-on-resumedr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cells#reset-cells#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsforce-hpdddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowlabellinux,codedebounce-intervallinux,input-typepriorityreset-gpiosvin-supplyenable-active-highgpiorockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecbrightness-levelsdefault-brightness-levelenable-gpiosbacklight-boot-offpwmspwm-delay-uspower-supplycharger-typebacklightstartup-delay-us