8( google,veyron-mickey-rev8google,veyron-mickey-rev7google,veyron-mickey-rev6google,veyron-mickey-rev5google,veyron-mickey-rev4google,veyron-mickey-rev3google,veyron-mickey-rev2google,veyron-mickey-rev1google,veyron-mickey-rev0google,veyron-mickeygoogle,veyronrockchip,rk3288&7Google Mickeyaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rV bcpu@501cpuarm,cortex-a12'@5<rbcpu@502cpuarm,cortex-a12'@5<rbcpu@503cpuarm,cortex-a12'@5<rbcpu-opp-tableoperating-points-v2jbopp-126000000u| opp-216000000u | opp-408000000uQ| opp-600000000u#F| opp-696000000u)||~opp-816000000u0,|B@opp-1008000000u<|opp-1200000000uG|opp-1416000000uTfr|Oopp-1512000000uZJ|opp-1608000000u_"| opp-1704000000ue|popp-1800000000ukI|\bus simple-busdma-controller@ff250000arm,pl330arm,primecell%@5 apb_pclkbdma-controller@ff600000arm,pl330arm,primecell`@5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@5 apb_pclkb_reserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mb timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5 a timerpclkdisplay-subsystemrockchip,display-subsystem5 mmc@ff0c0000rockchip,rk3288-dw-mshc;р 5Drvbiuciuciu-driveciu-sampleI  @Treset disabledmmc@ff0d0000rockchip,rk3288-dw-mshc;р 5Eswbiuciuciu-driveciu-sampleI ! @Tresetokay`j{ default mmc@ff0e0000rockchip,rk3288-dw-mshc;р 5Ftxbiuciuciu-driveciu-sampleI "@Treset disabledmmc@ff0f0000rockchip,rk3288-dw-mshc;р 5Guybiuciuciu-driveciu-sampleI #@Tresetokay`/MXdefault saradc@ff100000rockchip,saradc $g5I[saradcapb_pclkW Tsaradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclky  ~txrx ,default disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclky ~txrx -default disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclky~txrx .default !"#okay flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault$okay2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault% disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault& disabled2,i2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault' disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 75MUbaudclkapb_pclky~txrxdefault ()*okaybluetoothdefault +,-brcm,bcm43540-bt  . . ,.@-Jserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 85NVbaudclkapb_pclky~txrxdefault/okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 95OWbaudclkapb_pclkdefault0okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :5PXbaudclkapb_pclky~txrxdefault1 disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;5QYbaudclkapb_pclky  ~txrxdefault2 disabledthermal-zonesreserve_thermalaw3cpu_thermaladw3tripscpu_crit_ criticalcpu_alert_almost_warmpassivecpu_alert_warmpassiveb4cpu_alert_almost_hot8passiveb6cpu_alert_hot@Ppassiveb7cpu_alert_hotterH passiveb8cpu_alert_very_hotLpassiveb9cooling-mapscpu_warm_limit_cpu40cpu_warm_limit_gpu4 5cpu_almost_hot_limit_cpu60cpu_hot_limit_cpu70cpu_hotter_limit_cpu80cpu_very_hot_limit_cpu90cpu_very_hot_limit_gpu9 5gpu_thermaladw3tripsgpu_crit_ criticalgpu_alert_warmish`passiveb:gpu_alert_warmpassiveb;gpu_alert_hotterH passiveb<gpu_alert_very_very_hotOpassiveb=cooling-mapsgpu_warmish_limit_gpu: 5gpu_warm_limit_cpu;0gpu_hotter_limit_gpu< 5gpu_very_very_hot_limit_gpu= 5tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk Ttsadc-apbinitdefaultsleep>?>@Hokay%b3ethernet@ff290000rockchip,rk3288-gmac)@macirqeth_wake_irq@85fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB Tstmmaceth disabledusb@ff500000 generic-ehciP 5PAUusb disabled_usb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otguhostPB Uusb2-phy} disabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otguhost@@ PC Uusb2-phyokayzCusb@ff5c0000 generic-ehci\ 5 disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5LdefaultDokay2dpmic@1brockchip,rk808xin32kwifibt_32kin&Edefault FGH#1=IUamyIJ JbregulatorsDCDC_REG1vdd_arm q qb regulator-state-memDCDC_REG2vdd_gpu 5qb{regulator-state-memDCDC_REG3 vcc135_ddrregulator-state-mem0DCDC_REG4vcc_18w@w@bregulator-state-mem0Hw@LDO_REG3vdd_10B@B@regulator-state-mem0HB@LDO_REG7 vdd10_lcdB@B@dSWITCH_REG1 vcc33_lcdb^regulator-state-memLDO_REG8w@w@ vcc18_lcddi2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultK disabled2 pwm@ff680000rockchip,rk3288-pwmhdefaultL5_pwm disabledpwm@ff680010rockchip,rk3288-pwmhdefaultM5_pwmokaybpwm@ff680020rockchip,rk3288-pwmh defaultN5_pwm disabledpwm@ff680030rockchip,rk3288-pwmh0defaultO5_pwm disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsbpower-controller!rockchip,rk3288-power-controllerh bbpd_vio@9 5chgfdehilkj$PQRSTUVWXpd_hevc@11 5opYZpd_video@12 5[pd_gpu@13 5\]reboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv@Hjk$#gׄeрxhрxhbsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwb@edp-phyrockchip,rk3288-dp-phy5h24m disabledbrio-domains"rockchip,rk3288-io-voltage-domainokayI(6IFIT^`usbphyrockchip,rk3288-usb-phyokayusb-phy@320 5]phyclk Tphy-resetbCusb-phy@33445^phyclk Tphy-resetbAusb-phy@348H5_phyclk Tphy-resetbBwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdifl5T mclkhclky_~tx 6default`@ disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2sl 55Ri2s_clki2s_hclky__~txrxdefaulta}okaybcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk Tcrypto-rstokayiommu@ff900800rockchip,iommu@ @iep_mmu5 aclkiface disablediommu@ff914000rockchip,iommu @P @isp_mmu5 aclkiface disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclkb ilm Tcoreaxiahbvop@ff930000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vopb def Taxiahbdclkcokayportb endpoint@0dbwendpoint@1ebsendpoint@2fbmendpoint@3gbpiommu@ff930300rockchip,iommu  @vopb_mmu5 aclkifaceb okaybcvop@ff940000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vopb  Taxiahbdclkh disabledportb endpoint@0ibxendpoint@1jbtendpoint@2kbnendpoint@3lbqiommu@ff940300rockchip,iommu  @vopl_mmu5 aclkifaceb  disabledbhmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclkb @ disabledportsportendpoint@0mbfendpoint@1nbklvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdcob @ disabledportsport@0endpoint@0pbgendpoint@1qbldp@ff970000rockchip,rk3288-dp@ b5icdppclkPrUdpoTdp@ disabledportsport@0endpoint@0sbeendpoint@1tbjhdmi@ff980000rockchip,rk3288-dw-hdmil@ g5hmniahbisfrcecb okaydefaultunwedgeuvbportsportendpoint@0wbdendpoint@1xbivideo-codec@ff9a0000rockchip,rk3288-vpu   @vepuvdpu5 aclkhclkyb iommu@ff9a0800rockchip,iommu @vpu_mmu5 aclkifaceb byiommu@ff9c0440rockchip,iommu @@@ o @hevc_mmu5 aclkiface disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ @jobmmugpu5zb okay{b5gpu-opp-tableoperating-points-v2bzopp-100000000u|~opp-200000000u |~opp-300000000u|B@opp-400000000uׄ|opp-600000000u#F|qos@ffaa0000syscon b\qos@ffaa0080syscon b]qos@ffad0000syscon bQqos@ffad0100syscon bRqos@ffad0180syscon bSqos@ffad0400syscon bTqos@ffad0480syscon bUqos@ffad0500syscon bPqos@ffad0800syscon bVqos@ffad0880syscon bWqos@ffad0900syscon bXqos@ffae0000syscon b[qos@ffaf0000syscon bYqos@ffaf0080syscon bZefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400  @ @ `   bpinctrlrockchip,rk3288-pinctrl@default |}~gpio0@ff750000rockchip,gpio-banku Q5@ 1 A  | MPMIC_SLEEP_APPMIC_INT_LPOWER_BUTTON_LRECOVERY_SW_LOT_RESETAP_WARM_RESET_HI2C0_SDA_PMICI2C0_SCL_PMICnFALUTbEgpio1@ff780000rockchip,gpio-bankx R5A 1 A  gpio2@ff790000rockchip,gpio-banky S5B 1 A  0 MCONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_Lbgpio3@ff7a0000rockchip,gpio-bankz T5C 1 A   MFLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio4@ff7b0000rockchip,gpio-bank{ U5D 1 A   MUART0_RXDUART0_TXDUART0_CTS_LUART0_RTS_LSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEb.gpio5@ff7c0000rockchip,gpio-bank| V5E 1 A  gpio6@ff7d0000rockchip,gpio-bank} W5F 1 A  gpio7@ff7e0000rockchip,gpio-bank~ X5G 1 A   MPWM_LOGTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LCPU_NMIDVSOKHDMI_WAKEPOWER_HDMI_ONDVS1DVS2HDMI_CECI2C5_SDA_HDMII2C5_SCL_HDMIUART2_RXDUART2_TXDbJgpio8@ff7f0000rockchip,gpio-bank Y5H 1 A  ^ MRAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 ]hdmi-cec-c7 ]hdmi-ddc ]buhdmi-ddc-unwedge ]bvpower-hdmi-on ] bpcfg-output-low kbpcfg-pull-up vbpcfg-pull-down bpcfg-pull-none bpcfg-pull-none-12ma  bsleepglobal-pwroff ]b~ddrio-pwroff ]b}ddr0-retention ]b|ddr1-retention ]edpedp-hpd ] i2c0i2c0-xfer ]bDi2c1i2c1-xfer ]b$i2c2i2c2-xfer ]  bKi2c3i2c3-xfer ]b%i2c4i2c4-xfer ]b&i2c5i2c5-xfer ]b'i2s0i2s0-bus` ]balcdclcdc-ctl@ ]bosdmmcsdmmc-clk ]sdmmc-cmd ]sdmmc-cd ]sdmmc-bus1 ]sdmmc-bus4@ ]sdio0sdio0-bus1 ]sdio0-bus4@ ]bsdio0-cmd ]bsdio0-clk ]bsdio0-cd ]sdio0-wp ]sdio0-pwr ]sdio0-bkpwr ]sdio0-int ]wifienable-h ]bbt-enable-l ]b,bt-host-wake ]bt-host-wake-l ]b+bt-dev-wake-sleep ]bt-dev-wake-awake ]bt-dev-wake ]b-sdio1sdio1-bus1 ]sdio1-bus4@ ]sdio1-cd ]sdio1-wp ]sdio1-bkpwr ]sdio1-int ]sdio1-cmd ]sdio1-clk ]sdio1-pwr ] emmcemmc-clk ]bemmc-cmd ]bemmc-pwr ] emmc-bus1 ]emmc-bus4@ ]emmc-bus8 ]bemmc-reset ] bspi0spi0-clk ] bspi0-cs0 ] bspi0-tx ]bspi0-rx ]bspi0-cs1 ]spi1spi1-clk ] bspi1-cs0 ] bspi1-rx ]bspi1-tx ]bspi2spi2-cs1 ]spi2-clk ]b spi2-cs0 ]b#spi2-rx ]b"spi2-tx ] b!uart0uart0-xfer ]b(uart0-cts ]b)uart0-rts ]b*uart1uart1-xfer ] b/uart1-cts ] uart1-rts ] uart2uart2-xfer ]b0uart3uart3-xfer ]b1uart3-cts ] uart3-rts ] uart4uart4-xfer ]b2uart4-cts ] uart4-rts ] tsadcotp-gpio ] b>otp-out ] b?pwm0pwm0-pin ]bLpwm1pwm1-pin ]bMpwm2pwm2-pin ]bNpwm3pwm3-pin ]bOgmacrgmii-pins ] rmii-pins ]spdifspdif-tx ] b`pcfg-pull-none-drv-8ma  bpcfg-pull-up-drv-8ma v pcfg-output-high bbuttonspwr-key-l ]bpmicpmic-int-l ]bFdvs-1 ] bGdvs-2 ]bHrebootap-warm-reset-h ] brecovery-switchrec-mode-l ] tpmtpm-int-h ]write-protectfw-wp-ap ]chosen serial2:115200n8memorymemorypower-button gpio-keysdefaultpower Power E t d#gpio-restart gpio-restart E default emmc-pwrseqmmc-pwrseq-emmcdefault bsdio-pwrseqmmc-pwrseq-simple5 ext_clockdefault .b vcc-5vregulator-fixedvcc_5vLK@LK@ bvcc33-sysregulator-fixed vcc33_sys2Z2Zbvcc50-hdmiregulator-fixed vcc50_hdmi   J defaultvdd-logicpwm-regulator vdd_logic ! & 1{ E~pvcc33_ioregulator-fixed vcc33_io bIsound!rockchip,rockchip-audio-max98090 XVEYRON-HDMI g { #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthhost-wakeup-gpiosshutdown-gpiosdevice-wakeup-gpiosmax-speedbrcm,bt-pcm-int-paramspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvddio-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,hdmi-codecrockchip,i2s-controller