=8( u]incostartec,omap3-lilly-dbb056incostartec,omap3-lilly-a83xti,omap3630ti,omap36xxti,omap3 +"7INCOstartec LILLY-DBB056 (DM3730)chosenA=console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0aliasesF/ocp@68000000/i2c@48070000K/ocp@68000000/i2c@48072000P/ocp@68000000/i2c@48060000U/ocp@68000000/serial@4806a000]/ocp@68000000/serial@4806c000e/ocp@68000000/serial@49020000m/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8ucpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+4Qdefault_pinmux_uart1_pins iLNPR}pinmux_uart2_pinsi@B}pinmux_uart3_pinsinp}pinmux_i2c1_pinsi}pinmux_i2c2_pinsi}pinmux_i2c3_pinsi}pinmux_hsusb1_pinsi}pinmux_hsusb_otg_pins`irtvxz|~}pinmux_mmc1_pins0i}pinmux_spi2_pins i}pinmux_twl4030_pinsiA}pinmux_lan9117_pinsi}pinmux_gpio4_pinsi}pinmux_gpio5_pinsi\}pinmux_lcd_pinsi}pinmux_mmc2_pins`i(*,.02468:jl}pinmux_spi1_pins i}scm_conf@270sysconsimple-busp0+ p0}pbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-}clocks+mcbsp5_mux_fck@68ti,composite-mux-clockh} mcbsp5_fckti,composite-clock }mcbsp1_mux_fck@4ti,composite-mux-clock} mcbsp1_fckti,composite-clock }mcbsp2_mux_fck@4ti,composite-mux-clock }mcbsp2_fckti,composite-clock}mcbsp3_mux_fck@68ti,composite-mux-clock h}mcbsp3_fckti,composite-clock}mcbsp4_mux_fck@68ti,composite-mux-clock h}mcbsp4_fckti,composite-clock}clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+4Qdefaultpinmux_lan9221_pinsiZ}pinmux_tsc2048_pinsi}pinmux_mmc1cd_pinsiV}pinmux_twl4030_vpins i}aes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockY}osc_sys_ck@d40 ti,mux-clock @}sys_ck@1270ti,divider-clockp} sys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clock&1dpll3_m2x2_ckfixed-factor-clock&1}dpll4_x2_ckfixed-factor-clock&1corex2_fckfixed-factor-clock&1}!wkup_l4_ickfixed-factor-clock &1}Pcorex2_d3_fckfixed-factor-clock!&1}corex2_d5_fckfixed-factor-clock!&1}clockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock}Bvirt_12m_ck fixed-clock}virt_13m_ck fixed-clock]@}virt_19200000_ck fixed-clock$}virt_26000000_ck fixed-clock}virt_38_4m_ck fixed-clockI}dpll4_ck@d00ti,omap3-dpll-per-j-type-clock  D 0}dpll4_m2_ck@d48ti,divider-clock? H}"dpll4_m2x2_mul_ckfixed-factor-clock"&1}#dpll4_m2x2_ck@d00ti,hsdiv-gate-clock# ;}$omap_96m_alwon_fckfixed-factor-clock$&1}+dpll3_ck@d00ti,omap3-dpll-core-clock  @ 0}dpll3_m3_ck@1140ti,divider-clock@}%dpll3_m3x2_mul_ckfixed-factor-clock%&1}&dpll3_m3x2_ck@d00ti,hsdiv-gate-clock&  ;}'emu_core_alwon_ckfixed-factor-clock'&1}dsys_altclk fixed-clock}0mcbsp_clks fixed-clock}dpll3_m2_ck@d40ti,divider-clock @}core_ckfixed-factor-clock&1}(dpll1_fck@940ti,divider-clock( @})dpll1_ck@904ti,omap3-dpll-clock )  $ @ 4}dpll1_x2_ckfixed-factor-clock&1}*dpll1_x2m2_ck@944ti,divider-clock* D}>cm_96m_fckfixed-factor-clock+&1},omap_96m_fck@d40 ti,mux-clock,  @}Gdpll4_m3_ck@e40ti,divider-clock @}-dpll4_m3x2_mul_ckfixed-factor-clock-&1}.dpll4_m3x2_ck@d00ti,hsdiv-gate-clock. ;}/omap_54m_fck@d40 ti,mux-clock/0 @}:cm_96m_d2_fckfixed-factor-clock,&1}1omap_48m_fck@d40 ti,mux-clock10 @}2omap_12m_fckfixed-factor-clock2&1}Idpll4_m4_ck@e40ti,divider-clock@}3dpll4_m4x2_mul_ckti,fixed-factor-clock3Q_l}4dpll4_m4x2_ck@d00ti,gate-clock4 ;l}dpll4_m5_ck@f40ti,divider-clock?@}5dpll4_m5x2_mul_ckti,fixed-factor-clock5Q_l}6dpll4_m5x2_ck@d00ti,hsdiv-gate-clock6 ;l}ldpll4_m6_ck@1140ti,divider-clock?@}7dpll4_m6x2_mul_ckfixed-factor-clock7&1}8dpll4_m6x2_ck@d00ti,hsdiv-gate-clock8 ;}9emu_per_alwon_ckfixed-factor-clock9&1}eclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock( p};clkout2_src_mux_ck@d70ti,composite-mux-clock( ,: p}<clkout2_src_ckti,composite-clock;<}=sys_clkout2@d70ti,divider-clock=@ pmpu_ckfixed-factor-clock>&1}?arm_fck@924ti,divider-clock? $emu_mpu_alwon_ckfixed-factor-clock?&1}fl3_ick@a40ti,divider-clock( @}@l4_ick@a40ti,divider-clock@ @}Arm_ick@c40ti,divider-clockA @gpt10_gate_fck@a00ti,composite-gate-clock   }Cgpt10_mux_fck@a40ti,composite-mux-clockB  @}Dgpt10_fckti,composite-clockCDgpt11_gate_fck@a00ti,composite-gate-clock   }Egpt11_mux_fck@a40ti,composite-mux-clockB  @}Fgpt11_fckti,composite-clockEFcore_96m_fckfixed-factor-clockG&1}mmchs2_fck@a00ti,wait-gate-clock }mmchs1_fck@a00ti,wait-gate-clock }i2c3_fck@a00ti,wait-gate-clock }i2c2_fck@a00ti,wait-gate-clock }i2c1_fck@a00ti,wait-gate-clock }mcbsp5_gate_fck@a00ti,composite-gate-clock  } mcbsp1_gate_fck@a00ti,composite-gate-clock  } core_48m_fckfixed-factor-clock2&1}Hmcspi4_fck@a00ti,wait-gate-clockH }mcspi3_fck@a00ti,wait-gate-clockH }mcspi2_fck@a00ti,wait-gate-clockH }mcspi1_fck@a00ti,wait-gate-clockH }uart2_fck@a00ti,wait-gate-clockH }uart1_fck@a00ti,wait-gate-clockH  }core_12m_fckfixed-factor-clockI&1}Jhdq_fck@a00ti,wait-gate-clockJ }core_l3_ickfixed-factor-clock@&1}Ksdrc_ick@a10ti,wait-gate-clockK }gpmc_fckfixed-factor-clockK&1core_l4_ickfixed-factor-clockA&1}Lmmchs2_ick@a10ti,omap3-interface-clockL }mmchs1_ick@a10ti,omap3-interface-clockL }hdq_ick@a10ti,omap3-interface-clockL }mcspi4_ick@a10ti,omap3-interface-clockL }mcspi3_ick@a10ti,omap3-interface-clockL }mcspi2_ick@a10ti,omap3-interface-clockL }mcspi1_ick@a10ti,omap3-interface-clockL }i2c3_ick@a10ti,omap3-interface-clockL }i2c2_ick@a10ti,omap3-interface-clockL }i2c1_ick@a10ti,omap3-interface-clockL }uart2_ick@a10ti,omap3-interface-clockL }uart1_ick@a10ti,omap3-interface-clockL  }gpt11_ick@a10ti,omap3-interface-clockL  }gpt10_ick@a10ti,omap3-interface-clockL  }mcbsp5_ick@a10ti,omap3-interface-clockL  }mcbsp1_ick@a10ti,omap3-interface-clockL  }omapctrl_ick@a10ti,omap3-interface-clockL }dss_tv_fck@e00ti,gate-clock:}dss_96m_fck@e00ti,gate-clockG}dss2_alwon_fck@e00ti,gate-clock }dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock  }Mgpt1_mux_fck@c40ti,composite-mux-clockB  @}Ngpt1_fckti,composite-clockMN}aes2_ick@a10ti,omap3-interface-clockL }wkup_32k_fckfixed-factor-clockB&1}Ogpio1_dbck@c00ti,gate-clockO }sha12_ick@a10ti,omap3-interface-clockL }wdt2_fck@c00ti,wait-gate-clockO }wdt2_ick@c10ti,omap3-interface-clockP }wdt1_ick@c10ti,omap3-interface-clockP }gpio1_ick@c10ti,omap3-interface-clockP }omap_32ksync_ick@c10ti,omap3-interface-clockP }gpt12_ick@c10ti,omap3-interface-clockP }gpt1_ick@c10ti,omap3-interface-clockP }per_96m_fckfixed-factor-clock+&1} per_48m_fckfixed-factor-clock2&1}Quart3_fck@1000ti,wait-gate-clockQ }gpt2_gate_fck@1000ti,composite-gate-clock }Rgpt2_mux_fck@1040ti,composite-mux-clockB @}Sgpt2_fckti,composite-clockRS} gpt3_gate_fck@1000ti,composite-gate-clock }Tgpt3_mux_fck@1040ti,composite-mux-clockB @}Ugpt3_fckti,composite-clockTUgpt4_gate_fck@1000ti,composite-gate-clock }Vgpt4_mux_fck@1040ti,composite-mux-clockB @}Wgpt4_fckti,composite-clockVWgpt5_gate_fck@1000ti,composite-gate-clock }Xgpt5_mux_fck@1040ti,composite-mux-clockB @}Ygpt5_fckti,composite-clockXYgpt6_gate_fck@1000ti,composite-gate-clock }Zgpt6_mux_fck@1040ti,composite-mux-clockB @}[gpt6_fckti,composite-clockZ[gpt7_gate_fck@1000ti,composite-gate-clock }\gpt7_mux_fck@1040ti,composite-mux-clockB @}]gpt7_fckti,composite-clock\]gpt8_gate_fck@1000ti,composite-gate-clock  }^gpt8_mux_fck@1040ti,composite-mux-clockB @}_gpt8_fckti,composite-clock^_gpt9_gate_fck@1000ti,composite-gate-clock  }`gpt9_mux_fck@1040ti,composite-mux-clockB @}agpt9_fckti,composite-clock`aper_32k_alwon_fckfixed-factor-clockB&1}bgpio6_dbck@1000ti,gate-clockb}gpio5_dbck@1000ti,gate-clockb}gpio4_dbck@1000ti,gate-clockb}gpio3_dbck@1000ti,gate-clockb}gpio2_dbck@1000ti,gate-clockb }wdt3_fck@1000ti,wait-gate-clockb }per_l4_ickfixed-factor-clockA&1}cgpio6_ick@1010ti,omap3-interface-clockc}gpio5_ick@1010ti,omap3-interface-clockc}gpio4_ick@1010ti,omap3-interface-clockc}gpio3_ick@1010ti,omap3-interface-clockc}gpio2_ick@1010ti,omap3-interface-clockc }wdt3_ick@1010ti,omap3-interface-clockc }uart3_ick@1010ti,omap3-interface-clockc }uart4_ick@1010ti,omap3-interface-clockc}gpt9_ick@1010ti,omap3-interface-clockc }gpt8_ick@1010ti,omap3-interface-clockc }gpt7_ick@1010ti,omap3-interface-clockc}gpt6_ick@1010ti,omap3-interface-clockc}gpt5_ick@1010ti,omap3-interface-clockc}gpt4_ick@1010ti,omap3-interface-clockc}gpt3_ick@1010ti,omap3-interface-clockc}gpt2_ick@1010ti,omap3-interface-clockc}mcbsp2_ick@1010ti,omap3-interface-clockc}mcbsp3_ick@1010ti,omap3-interface-clockc}mcbsp4_ick@1010ti,omap3-interface-clockc}mcbsp2_gate_fck@1000ti,composite-gate-clock}mcbsp3_gate_fck@1000ti,composite-gate-clock}mcbsp4_gate_fck@1000ti,composite-gate-clock}emu_src_mux_ck@1140 ti,mux-clock def@}gemu_src_ckti,clkdm-gate-clockg}hpclk_fck@1140ti,divider-clockh@pclkx2_fck@1140ti,divider-clockh@atclk_fck@1140ti,divider-clockh@traceclk_src_fck@1140 ti,mux-clock def@}itraceclk_fck@1140ti,divider-clocki @secure_32k_fck fixed-clock}jgpt12_fckfixed-factor-clockj&1} wdt1_fckfixed-factor-clockj&1security_l4_ick2fixed-factor-clockA&1}kaes1_ick@a14ti,omap3-interface-clockk rng_ick@a14ti,omap3-interface-clockk }sha11_ick@a14ti,omap3-interface-clockk des1_ick@a14ti,omap3-interface-clockk cam_mclk@f00ti,gate-clockllcam_ick@f10!ti,omap3-no-wait-interface-clockA}csi2_96m_fck@f00ti,gate-clock}security_l3_ickfixed-factor-clock@&1}mpka_ick@a14ti,omap3-interface-clockm icr_ick@a10ti,omap3-interface-clockL des2_ick@a10ti,omap3-interface-clockL mspro_ick@a10ti,omap3-interface-clockL mailboxes_ick@a10ti,omap3-interface-clockL ssi_l4_ickfixed-factor-clockA&1}tsr1_fck@c00ti,wait-gate-clock  }sr2_fck@c00ti,wait-gate-clock  }sr_l4_ickfixed-factor-clockA&1dpll2_fck@40ti,divider-clock(@}ndpll2_ck@4ti,omap3-dpll-clock n$@4}odpll2_m2_ck@44ti,divider-clockoD}piva2_ck@0ti,wait-gate-clockp}modem_fck@a00ti,omap3-interface-clock  }sad2d_ick@a10ti,omap3-interface-clock@ }mad2d_ick@a18ti,omap3-interface-clock@ }mspro_fck@a00ti,wait-gate-clock ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock! }qssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock! @$}rssi_ssr_fck_3430es2ti,composite-clockqr}sssi_sst_fck_3430es2fixed-factor-clocks&1}hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clockK }ssi_ick_3430es2@a10ti,omap3-ssi-interface-clockt }usim_gate_fck@c00ti,composite-gate-clockG  }sys_d2_ckfixed-factor-clock &1}vomap_96m_d2_fckfixed-factor-clockG&1}womap_96m_d4_fckfixed-factor-clockG&1}xomap_96m_d8_fckfixed-factor-clockG&1}yomap_96m_d10_fckfixed-factor-clockG&1 }zdpll5_m2_d4_ckfixed-factor-clocku&1}{dpll5_m2_d8_ckfixed-factor-clocku&1}|dpll5_m2_d16_ckfixed-factor-clocku&1}}dpll5_m2_d20_ckfixed-factor-clocku&1}~usim_mux_fck@c40ti,composite-mux-clock( vwxyz{|}~ @}usim_fckti,composite-clockusim_ick@c10ti,omap3-interface-clockP  }dpll5_ck@d04ti,omap3-dpll-clock   $ L 4}dpll5_m2_ck@d50ti,divider-clock P}usgx_gate_fck@b00ti,composite-gate-clock( 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}dss1_alwon_fck_3430es2@e00ti,dss-gate-clockl}dss_ick_3430es2@e10ti,omap3-dss-interface-clockA}usbhost_120m_fck@1400ti,gate-clocku}usbhost_48m_fck@1400ti,dss-gate-clock2}usbhost_ick@1410ti,omap3-dss-interface-clockA}uart4_fck@1000ti,wait-gate-clockQ}clockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainlemu_clkdmti,clockdomainhdpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomainod2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain target-module@48320000ti,sysc-omap2ti,syscH2H2 revsyscOfckick+ H2counter@0ti,omap-counter32k interrupt-controller@48200000ti,omap3-intcH }target-module@48056000ti,sysc-omap2ti,syscH`H`,H`(revsyscsyss#  Kick+ H`dma-controller@0ti,omap3630-sdmati,omap-sdma  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XPspi@480b8000ti,omap2-mcspiH [+mcspi3y tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi4yFGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>txrx" /8DPQdefault_Zgxmmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrxokayPD / Qdefault_mmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuH mmu_isp}mmu@5d000000ti,omap2-iommu]mmu_iva disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< commontxrxmcbsp1 txrxfck disabledtarget-module@480a0000ti,sysc-omap2ti,syscH <H @H Drevsyscsyssick+ H rng@0 ti,omap2-rng 4mcbsp@49022000ti,omap3-mcbspI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxfckickokay}mcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrxfckick disabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 commontxrxmcbsp4txrxfck disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR commontxrxmcbsp5txrxfck disabledsham@480c3000ti,omap3-shamshamH 0d1Erxtarget-module@48318000ti,sysc-omap2-timerti,syscH1H1H1revsyscsyss' fckick+ H1timer@0ti,omap3430-timerfck%Btarget-module@49032000ti,sysc-omap2-timerti,syscI I I revsyscsyss'  fckick+ I timer@0ti,omap3430-timer&timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer55timer@4903a000ti,omap3430-timerI*timer65timer@4903c000ti,omap3430-timerI+timer75timer@4903e000ti,omap3430-timerI,timer8B5timer@49040000ti,omap3430-timerI-timer9Btimer@48086000ti,omap3430-timerH`.timer10Btimer@48088000ti,omap3430-timerH/timer11Btarget-module@48304000ti,sysc-omap2-timerti,syscH0@H0@H0@revsyscsyss'  fckick+ H0@timer@0ti,omap3430-timer_Ousbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+Qdefault_ _ iehci-phyohci@48064400ti,ohci-omap3HDLtehci@48064800 ti,ehci-omapHHM gpmc@6e000000ti,omap3430-gpmcgpmcnrxtx+FV00 } nand@0,0ti,omap2-nand   bch8*8dJd\kd~dKKdd<-G2aKy+partition@0MLOpartition@80000u-bootpartition@260000u-boot-environment&partition@280000kernel(Ppartition@780000 filesystemxethernet@7,0smsc,lan9221smsc,lan9115* 8<J<\k ~  < <dd2GKayK-  Qdefault_miiethernet@4,0smsc,lan9117smsc,lan9115* 8AJA\k ~  A Add<GKayK-  Qdefault_miiusb_otg_hs@480ab000ti,omap3-musbH \]mcdma usb_otg_hs    Qdefault_  - 5usb2-phy ?2dss@48050000 ti,omap3-dssH disabled dss_corefck+dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH  disabled dss_vencfcktv_dac_clkssi-controller@48058000 ti,omap3-ssissiokHHsysgddGgdd_mpu+ s ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFserial@49042000ti,omap3-uartI PQRtxrxuart4l disabledregulator-abb-mpu ti,abb-v1 abb_mpu_iva+H0rH0hbase-addressint-address E  ^ o` sO7}pinmux@480025a0 ti,omap3-padconfpinctrl-singleH%\+4Qdefaultpinmux_hsusb1_2_pins`i8:<>@BDFHJLN} pinmux_gpio1_pinsiZ }isp@480bc000 ti,omap3-ispH H   ports+bandgap@48002524H%$ti,omap36xx-bandgap }target-module@480cb000ti,sysc-omap3630-srti,syscsmartreflex_coreH 8sysc fck+ H smartreflex@0ti,omap3-smartreflex-coretarget-module@480c9000ti,sysc-omap3630-srti,syscsmartreflex_mpu_ivaH 8sysc fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivatarget-module@50000000ti,sysc-omap4ti,syscPP revsysc  fckick+ Popp-tableoperating-points-v2-ti-cpu}opp50-300000000  ssssss  opp100-600000000 #F OOOOOO opp130-800000000 / 777777 opp1g-1000000000 ;   opp_supplyti,omap-opp-supply thermal-zonescpu_thermal  " 0N  =memory@80000000umemoryleds gpio-ledsled1lilly-a83x::led1 2 Mdefault-onsoundti,omap-twl4030 clilly-a83x lvcc3regulator-fixedVCC32Z2Z}hsusb1_phyusb-nop-xceiv}  compatibleinterrupt-parent#address-cells#size-cellsmodelbootargsi2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersreg-namesti,sysc-sidleti,sysc-maskti,sysc-midleti,syss-mask#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csstatusspi-max-frequencypendown-gpiovcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourceti,dual-voltpbias-supplycd-gpioscd-invertedvmmc-supplybus-widthcap-sdio-irqcap-sd-highspeedcap-mmc-highspeedwp-gpios#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-securenum-portsport1-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthti,nand-ecc-optgpmc,mux-add-datagpmc,device-widthgpmc,wait-pingpmc,wait-monitoring-nsgpmc,burst-lengthgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-delay-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nslabelbank-widthgpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthphy-modesmsc,force-internal-phymultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modeti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorslinux,default-triggerti,modelti,mcbsp