-H*H(*FVP Base RevCarm,fvp-base-revcarm,vexpress"1clock-24000000 fixed-clock=Jn6 Zv2m:clk24mhzmclock-1000000 fixed-clock=JB@Zv2m:refclk1mhzmclock-32768 fixed-clock=JZv2m:refclk32khzmregulator-3v3regulator-fixedu3V32Z2Zmmccarm,vexpress,config-busclock-controllerarm,vexpress-oscjep= Zv2m:oscclk1mresetarm,vexpress-resetmuxfpgaarm,vexpress-muxfpgashutdownarm,vexpress-shutdownrebootarm,vexpress-reboot dvimodearm,vexpress-dvimode bus@8000000 simple-bus"1 ?x2            !!""##$$%%&&''(())**++,,..motherboard-bus@8000000arm,vexpress,v2m-p1simple-bus"1x @rs2flash@0arm,vexpress-flashcfi-flashSWethernet@202000000smsc,lan91c111 Sbiofpga-bus@300000000 simple-bus"1!sysreg@10000arm,vexpress-sysregSm}msysctl@20000arm,sp810arm,primecellS refclktimclkapb_pclk=0Ztimerclken0timerclken1timerclken2timerclken3 maaci@40000arm,pl041arm,primecellSb  apb_pclkmmc@50000arm,pl180arm,primecellSb   mclkapb_pclkkmi@60000arm,pl050arm,primecellSb KMIREFCLKapb_pclkkmi@70000arm,pl050arm,primecellSb KMIREFCLKapb_pclkserial@90000arm,pl011arm,primecellS buartclkapb_pclkserial@a0000arm,pl011arm,primecellS buartclkapb_pclkserial@b0000arm,pl011arm,primecellS buartclkapb_pclkserial@c0000arm,pl011arm,primecellS buartclkapb_pclkwatchdog@f0000arm,sp805arm,primecellSbwdog_clkapb_pclktimer@110000arm,sp804arm,primecellSbtimclken1timclken2apb_pclktimer@120000arm,sp804arm,primecellSbtimclken1timclken2apb_pclkvirtio@130000 virtio,mmioSb*rtc@170000arm,pl031arm,primecellSb apb_pclkclcd@1f0000arm,pl111arm,primecellS combinedbclcdclkapb_pclk portendpoint  mvirtio@140000 virtio,mmioSb+virtio@150000 virtio,mmioSb,virtio@200000 virtio,mmioS b. 7disabledchosen>serial0:115200n8aliasesGJ/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@90000GR/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@a0000GZ/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@b0000Gb/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@c0000psci arm,psci-0.2jsmccpus"1cpu@0qcpu arm,armv8S}psci@@ cpu@100qcpu arm,armv8S}psci@@ cpu@200qcpu arm,armv8S}psci@@ cpu@300qcpu arm,armv8S}psci@@ cpu@10000qcpu arm,armv8S}psci@@ cpu@10100qcpu arm,armv8S}psci@@ cpu@10200qcpu arm,armv8S}psci@@ cpu@10300qcpu arm,armv8S}psci@@ l2-cache0cache@m l2-cache1cache@m memory@80000000qmemory Sreserved-memory"1vram@18000000shared-dma-poolSm interrupt-controller@2f000000 arm,gic-v3"1PS// , , ,  b mmsi-controller@2f020000*arm,gic-v3-itsS/5m timerarm,armv8-timer0b   pmuarm,armv8-pmuv3 bspe-pmu'arm,statistical-profiling-extension-v1 bpci@40000000"1pci-host-ecam-genericqpciDS@PP2N V`miommu@2b400000 arm,smmu-v3S+@0bJOKMeventqgerrorpriqcmdq-sync`{ mpanelarm,rtsm-displayportendpoint m  modelcompatibleinterrupt-parent#address-cells#size-cells#clock-cellsclock-frequencyclock-output-namesphandleregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onarm,vexpress,config-bridgearm,vexpress-sysreg,funcfreq-rangeranges#interrupt-cellsinterrupt-map-maskinterrupt-maparm,v2m-memory-mapregbank-widthinterruptsgpio-controller#gpio-cellsclocksclock-namesassigned-clocksassigned-clock-parentscd-gpioswp-gpiosmax-frequencyvmmc-supplyinterrupt-namesmemory-regionremote-endpointarm,pl11x,tft-r0g0b0-padsstatusstdout-pathserial0serial1serial2serial3methoddevice_typeenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecache-levelcache-unifiedno-mapinterrupt-controller#msi-cellsmsi-controllerbus-rangemsi-mapiommu-mapdma-coherentats-supported#iommu-cellsmsi-parent