8 ($mediatek,mt8195-evbmediatek,mt8195 +!7MediaTek MT8195 evaluation boardaliases=/soc/mailbox@10320000B/soc/mailbox@10330000G/soc/serial@11001100cpus+cpu@0Ocpuarm,cortex-a55[_pscimec3@4 cpu@100Ocpuarm,cortex-a55[_pscimec3@4 cpu@200Ocpuarm,cortex-a55[_pscimec3@4 cpu@300Ocpuarm,cortex-a55[_pscimec3@4 cpu@400Ocpuarm,cortex-a78[_pscimf cpu@500Ocpuarm,cortex-a78[_pscimfcpu@600Ocpuarm,cortex-a78[_pscimfcpu@700Ocpuarm,cortex-a78[_pscimfcpu-mapcluster0core0 core1 core2 core3 core4 core5core6core7idle-statespscicpu-off-larm,idle-state2&_6Dcpu-off-barm,idle-state-&6cluster-off-larm,idle-state7&6Hcluster-off-barm,idle-state2&6l2-cache0cachel2-cache1cachel3-cachecachedsu-pmu arm,dsu-pmuG R Wfaildmic-codec dmic-codec^k2mt8195-sound{ Wdisabledfixed-factor-clock-13mfixed-factor-clockclk13m(oscillator-26m fixed-clockclk26moscillator-32k fixed-clockclk32kperformance-controller@11bc10mediatek,cpufreq-hw [ 0 pmu-a55arm,cortex-a55-pmu Gpmu-a78arm,cortex-a78-pmu Gpsci arm,psci-1.0fsmctimerarm,armv8-timer @G   soc+ simple-businterrupt-controller@c000000 arm,gic-v3  [   G ppi-partitionsinterrupt-partition-0' interrupt-partition-1' syscon@10000000 mediatek,mt8195-topckgensyscon[syscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfd[0syscon@10003000mediatek,mt8195-pericfgsyscon[01pinctrl@10005000mediatek,mt8195-pinctrl[PB=iocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleintGWcGi2c0-pins9pinso vei2c1-pins:pinso  vei2c4-pins;pinsovei2c6-pins7pinsovei2c7-pinspinsovenor-pins5pins0 opins1 ovuart0-pins.pinsobcsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd[`power-controller!mediatek,mt8195-power-controller+*power-domain@8[+power-domain@9[ mfg+power-domain@10[ power-domain@11[ power-domain@12[ power-domain@13[ power-domain@14[power-domain@15[ @AK   vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18+power-domain@24[vdec1-0power-domain@27[ venc1-larbpower-domain@16[8$%&'()Dvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5+power-domain@17[vppsys1vppsys1-0vppsys1-1power-domain@22[ $wepsys-0wepsys-1wepsys-2wepsys-3power-domain@23[ vdec0-0power-domain@25[!vdec2-0power-domain@26[" venc0-larbpower-domain@18[ ###&vdosys1vdosys1-0vdosys1-1vdosys1-2+power-domain@19[power-domain@20[power-domain@21[Qhdmi_txpower-domain@28[$$  img-0img-1+power-domain@29[power-domain@30[$%ipeipe-0ipe-1power-domain@31[(&&&&&cam-0cam-1cam-2cam-3cam-4+power-domain@32[ power-domain@33[!power-domain@34["power-domain@0[power-domain@1[power-domain@2[power-domain@3[power-domain@4[57csi_rx_topcsi_rx_top1power-domain@5[' etherpower-domain@6[Xn adspadsp1+power-domain@7[ g"n2audioaudio1audio2audio3watchdog@10007000mediatek,mt8195-wdt[p0-syscon@1000c000"mediatek,mt8195-apmixedsyssyscon[timer@10017000,mediatek,mt8195-timermediatek,mt6765-timer[pG (pwrap@10024000mediatek,mt8195-pwrapsyscon[@=pwrapG spiwrap$spmi@10027000mediatek,mt8195-spmi [p =pmifspmimstE(pmif_sys_ckpmif_tmr_ckspmimst_clk_mux$infra-iommu@10315000mediatek,mt8195-iommu-infra[1PPPG.mailbox@10320000mediatek,mt8195-gce[2@G;`mailbox@10330000mediatek,mt8195-gce[3@G;scp@10500000mediatek,mt8195-scp0[Prp=sramcfgl1tcmG Wdisabledclock-controller@10720000mediatek,mt8195-scp_adsp[r)dsp@10803000mediatek,mt8195-dsp [0 =cfgsram,Xn)#Kadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_hG*Urxtx`+, Wdisabledmailbox@10816000mediatek,mt8195-adsp-mbox;[`G+mailbox@10817000mediatek,mt8195-adsp-mbox;[pG,mt8195-afe-pcm@10890000mediatek,mt8195-audio[gG*G6y- audiosysg"#neabcd2)clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp Wdisabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart[G  baudbusWokaydefault.serial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart[G  baudbus Wdisabledserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart[G  baudbus Wdisabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart[G  baudbus Wdisabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart[G  baudbus Wdisabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart[G  baudbus Wdisabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc[ mainWokaysyscon@11003000"mediatek,mt8195-pericfg_aosyscon[0'spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+[Gparent-clksel-clkspi-clk Wdisabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+[G3parent-clksel-clkspi-clk Wdisabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+[ G4parent-clksel-clkspi-clk Wdisabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+[0G5parent-clksel-clkspi-clk Wdisabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+[G<parent-clksel-clkspi-clk Wdisabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+[G=parent-clksel-clkspi-clk Wdisabledspi@1101d000mediatek,mt8195-spi-slave[GRspi Wdisabledspi@1101e000mediatek,mt8195-spi-slave[GSspi Wdisabledusb@11200000'mediatek,mt8195-xhcimediatek,mtk-xhci [  > =macippcG/0,-$/B$sys_ckref_ckmcu_ckdma_ckxhci_ck 1gWokaymmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc [#Gsourcehclksource_cg Wdisabledmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc [$G$sourcehclksource_cg Wdisabledmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc [%G Isourcehclksource_cg  Wdisabledusb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci [))> =macippcG2./$''$sys_ckref_ckmcu_ckdma_ckxhci_ck 1hWokayusb@112a0000'mediatek,mt8195-xhcimediatek,mtk-xhci [**> =macippcG301 ''$sys_ckref_ckmcu_ckdma_ckxhci_ck 1iWokayusb@112b0000'mediatek,mt8195-xhcimediatek,mtk-xhci [++> =macippcG423 '' $sys_ckref_ckmcu_ckdma_ckxhci_ck 1jWokayspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor[2G9o'' spisfaxi+Wokaydefault5flash@0jedec,spi-nor[efuse@11c10000%mediatek,mt8195-efusemediatek,efuse[+usb3-tx-imp@184,1[Ausb3-rx-imp@184,2[@usb3-intr@185[?usb3-tx-imp@186,1[>usb3-rx-imp@186,2[=usb3-intr@187[<usb2-intr-p0@188,1[usb2-intr-p1@188,2[usb2-intr-p2@189,1[usb2-intr-p3@189,2[t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Wokayusb-phy@0[ref3t-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Wokayusb-phy@0[ref4i2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c ["G6; maindma+ Wdisabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c ["G6; maindma+Wokaydefault7i2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c [ "G6; maindma+ Wdisabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s[06i2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c ["G8; maindma+Wokaydefault9i2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c ["G8; maindma+Wokaydefault:i2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c [ "G8; maindma+ Wdisabledi2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c [0"G8; maindma+ Wdisabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c [@"G8; maindma+Wokaydefault;clock-controller@11e05000mediatek,mt8195-imp_iic_wrap_w[P8t-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+G*Wokayusb-phy@0[  refda_ref2usb-phy@700[ refda_ref <=>intrrx_imptx_impt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Wokayusb-phy@0[  refda_ref/usb-phy@700[ refda_ref ?@Aintrrx_imptx_imp0ufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy[ unipromp Wdisabledclock-controller@13fbf000mediatek,mt8195-mfgcfg[clock-controller@14000000mediatek,mt8195-vppsys0[smi@14010000mediatek,mt8195-smi-sub-common[apbsmigals00BG*Csmi@14011000mediatek,mt8195-smi-sub-common[apbsmigals00BG*_smi@14012000mediatek,mt8195-smi-common-vpp[  apbsmigals0gals1G*Blarb@14013000mediatek,mt8195-smi-larb[0=0CapbsmiG*Fiommu@14018000mediatek,mt8195-iommu-vpp[8NDEFGHIJKLMNOPQGRbclk.G*clock-controller@14e00000mediatek,mt8195-wpesys[clock-controller@14e02000mediatek,mt8195-wpesys_vpp0[ clock-controller@14e03000mediatek,mt8195-wpesys_vpp1[0larb@14e04000mediatek,mt8195-smi-larb[@=0RapbsmiG*elarb@14e05000mediatek,mt8195-smi-larb[P=0B apbsmigalsG*Hclock-controller@14f00000mediatek,mt8195-vppsys1[larb@14f02000mediatek,mt8195-smi-larb[ =0R apbsmigalsG*dlarb@14f03000mediatek,mt8195-smi-larb[0=0C apbsmigalsG*Gclock-controller@15000000mediatek,mt8195-imgsys[$larb@15001000mediatek,mt8195-smi-larb[= 0S$$$  apbsmigalsG*fsmi@15002000mediatek,mt8195-smi-sub-common[ $$apbsmigals00BG*Vsmi@15003000mediatek,mt8195-smi-sub-common[0$$$ apbsmigals00RG*Sclock-controller@15110000 mediatek,mt8195-imgsys1_dip_top[Tlarb@15120000mediatek,mt8195-smi-larb[= 0S$TapbsmiG*gclock-controller@15130000mediatek,mt8195-imgsys1_dip_nr[clock-controller@15220000mediatek,mt8195-imgsys1_wpe["Ularb@15230000mediatek,mt8195-smi-larb[#= 0S$UapbsmiG*hclock-controller@15330000mediatek,mt8195-ipesys[3%larb@15340000mediatek,mt8195-smi-larb[4= 0V%%apbsmiG*Iclock-controller@16000000mediatek,mt8195-camsys[&larb@16001000mediatek,mt8195-smi-larb[= 0W&&& apbsmigalsG*ilarb@16002000mediatek,mt8195-smi-larb[ =0X&&apbsmiG*Jsmi@16004000mediatek,mt8195-smi-sub-common[@&&&apbsmigals00RG*Wsmi@16005000mediatek,mt8195-smi-sub-common[P&&apbsmigals00BG*Xlarb@16012000mediatek,mt8195-smi-larb[ =0XYYapbsmiG* Klarb@16013000mediatek,mt8195-smi-larb[0=0WZZapbsmiG* jlarb@16014000mediatek,mt8195-smi-larb[@=0X[[apbsmiG*!Qlarb@16015000mediatek,mt8195-smi-larb[P=0W\\apbsmiG*!oclock-controller@1604f000mediatek,mt8195-camsys_rawa[Yclock-controller@1606f000mediatek,mt8195-camsys_yuva[Zclock-controller@1608f000mediatek,mt8195-camsys_rawb[[clock-controller@160af000mediatek,mt8195-camsys_yuvb[ \clock-controller@16140000mediatek,mt8195-camsys_mraw[]larb@16141000mediatek,mt8195-smi-larb[=0W&]& apbsmigalsG*"nlarb@16142000mediatek,mt8195-smi-larb[ =0X]]apbsmiG*"Pclock-controller@17200000mediatek,mt8195-ccusys[ ^larb@17201000mediatek,mt8195-smi-larb[ =0X^^apbsmiG*Llarb@1800d000mediatek,mt8195-smi-larb[=0R apbsmiG*mlarb@1800e000mediatek,mt8195-smi-larb[=0_ apbsmiG*Oclock-controller@1800f000mediatek,mt8195-vdecsys_soc[ larb@1802e000mediatek,mt8195-smi-larb[=0RapbsmiG*lclock-controller@1802f000mediatek,mt8195-vdecsys[larb@1803e000mediatek,mt8195-smi-larb[=0_!apbsmiG*Nclock-controller@1803f000mediatek,mt8195-vdecsys_core1[!clock-controller@190f3000mediatek,mt8195-apusys_pll[0clock-controller@1a000000mediatek,mt8195-vencsys["larb@1a010000mediatek,mt8195-smi-larb[=0R""apbsmiG*kclock-controller@1b000000mediatek,mt8195-vencsys_core1[syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon[ ``larb@1b010000mediatek,mt8195-smi-larb[=0B  apbsmigalsG*Movl@1c0000002mediatek,mt8195-disp-ovlmediatek,mt8183-disp-ovl[G|G*]ad`rdma@1c002000mediatek,mt8195-disp-rdma[ G~G*]ad` color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color[0GG*d`0ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr[@GG*d`@aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aal[PGG*d`Pgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma[`GG*d``dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-dither[pGG* d`pdsc@1c009000mediatek,mt8195-disp-dsc[GG*d`merge@1c014000mediatek,mt8195-disp-merge[@GG*d`@mutex@1c016000mediatek,mt8195-disp-mutex[`GG*|Ularb@1c018000mediatek,mt8195-smi-larb[=0R((  apbsmigalsG*blarb@1c019000mediatek,mt8195-smi-larb[=0B(  apbsmigalsG*Dsyscon@1c100000mediatek,mt8195-vdosys1syscon[#smi@1c01b000mediatek,mt8195-smi-common-vdo[ %&)$apbsmigals0gals1G*Riommu@1c01f000mediatek,mt8195-iommu-vdo[8NbcdefghijklmnoG.'bclkG*alarb@1c102000mediatek,mt8195-smi-larb[ =0R### apbsmigalsG*clarb@1c103000mediatek,mt8195-smi-larb[0=0B##  apbsmigalsG*Echosenserial0:921600n8memory@40000000Omemory[@ compatibleinterrupt-parent#address-cells#size-cellsmodelgce0gce1serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-upmediatek,drive-strength-advdrive-strengthbias-pull-down#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellspower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-namespinctrl-0#io-channel-cellsphysmediatek,syscon-wakeupwakeup-sourceusb2-lpm-disablespi-max-frequencybits#phy-cellsnvmem-cellsnvmem-cell-namesmediatek,smimediatek,larb-idmediatek,larbsiommusmediatek,gce-client-regmediatek,gce-eventsstdout-path