8 (%mediatek,mt8195-demomediatek,mt8195 +7MediaTek MT8195 demo boardaliases=/soc/mailbox@10320000B/soc/mailbox@10330000G/soc/serial@11001100cpus+cpu@0Ocpuarm,cortex-a55[_pscimec3@4 cpu@100Ocpuarm,cortex-a55[_pscimec3@4 cpu@200Ocpuarm,cortex-a55[_pscimec3@4 cpu@300Ocpuarm,cortex-a55[_pscimec3@4 cpu@400Ocpuarm,cortex-a78[_pscimf cpu@500Ocpuarm,cortex-a78[_pscimfcpu@600Ocpuarm,cortex-a78[_pscimfcpu@700Ocpuarm,cortex-a78[_pscimfcpu-mapcluster0core0 core1 core2 core3 core4 core5core6core7idle-statespscicpu-off-larm,idle-state2&_6Dcpu-off-barm,idle-state-&6cluster-off-larm,idle-state7&6Hcluster-off-barm,idle-state2&6l2-cache0cachel2-cache1cachel3-cachecachedsu-pmu arm,dsu-pmuG R Wfaildmic-codec dmic-codec^k2mt8195-sound{ Wdisabledfixed-factor-clock-13mfixed-factor-clockclk13m(oscillator-26m fixed-clockclk26moscillator-32k fixed-clockclk32kperformance-controller@11bc10mediatek,cpufreq-hw [ 0 pmu-a55arm,cortex-a55-pmu Gpmu-a78arm,cortex-a78-pmu Gpsci arm,psci-1.0fsmctimerarm,armv8-timer @G   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^volume_updssomemory@40000000Omemory[@reserved-memory+optee@43200000[C memory@50000000shared-dma-pool[Pmemory@53000000shared-dma-pool[S@memory@54600000[T` memory@60000000shared-dma-pool[`memory@62000000shared-dma-pool[b@ compatibleinterrupt-parent#address-cells#size-cellsmodelgce0gce1serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxinput-enablebias-pull-updrive-strengthbias-pull-down#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsinterrupts-extendedregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#iommu-cells#mbox-cellspower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-namespinctrl-0#io-channel-cellsphysmediatek,syscon-wakeupwakeup-sourcevusb33-supplyvbus-supplypinctrl-1bus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecd-gpioscap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104bits#phy-cellsinterrupt-namesrichtek,vinovp-microvoltregulator-compatibleLDO_VIN3-supplynvmem-cellsnvmem-cell-namesmediatek,smimediatek,larb-idmediatek,larbsiommusmediatek,gce-client-regmediatek,gce-eventsstdout-pathlabellinux,codedebounce-intervalno-map