8($mediatek,mt8192-evbmediatek,mt8192 +!7MediaTek MT8192 evaluation boardaliases=/soc/ovl@14005000B/soc/ovl@14006000J/soc/ovl@14014000R/soc/rdma@14007000X/soc/rdma@14015000^/soc/serial@11002000fixed-factor-clock-13mfixed-factor-clockfszclk13m$oscillator0 fixed-clockfclk26moscillator1 fixed-clockfclk32kcpus+cpu@0cpuarm,cortex-a55psciec3@  cpu@100cpuarm,cortex-a55psciec3@  cpu@200cpuarm,cortex-a55psciec3@  cpu@300cpuarm,cortex-a55psciec3@  cpu@400cpuarm,cortex-a76pscif  cpu@500cpuarm,cortex-a76pscif  cpu@600cpuarm,cortex-a76pscif  cpu@700cpuarm,cortex-a76pscif  cpu-mapcluster0core0 core1 core2 core3 core4 core5 core6 core7 l2-cache0cachel2-cache1cache l3-cachecacheidle-states$pscicpu-sleep-larm,idle-state1HY7jz cpu-sleep-barm,idle-state1HY#jzcluster-sleep-larm,idle-state1HY<jz\cluster-sleep-barm,idle-state1HY(jz pmu-a55arm,cortex-a55-pmu pmu-a76arm,cortex-a76-pmu psci arm,psci-1.0smctimerarm,armv8-timer @   ]@soc+ simple-busperformance-controller@11bc10mediatek,cpufreq-hw  0 interrupt-controller@c000000 arm,gic-v3     ppi-partitionsinterrupt-partition-0 interrupt-partition-1syscon@10000000 mediatek,mt8192-topckgensysconfsyscon@10001000 mediatek,mt8192-infracfgsysconfsyscon@10003000mediatek,mt8192-pericfgsyscon0f(pinctrl@10005000mediatek,mt8192-pinctrlP] iocfg0iocfg_rmiocfg_bmiocfg_bliocfg_briocfg_lmiocfg_lbiocfg_rtiocfg_ltiocfg_tleint$0syscon@10006000)mediatek,mt8192-scpsyssysconsimple-mfd`power-controller!mediatek,mt8192-power-controller+<*power-domain@0s:/Paudioaudio1audio2\<power-domain@1sPconn\<power-domain@2sPmfg+<power-domain@3\+<power-domain@4<power-domain@5<power-domain@6<power-domain@7<power-domain@8<power-domain@9 (s !Pdispdisp-0disp-1disp-2disp-3\+<power-domain@10 (sPipeipe-0ipe-1ipe-2ipe-3\<power-domain@11 sPispisp-0isp-1\<power-domain@12 sPisp2isp2-0isp2-1\<power-domain@13 s Pmdpmdp-0\<power-domain@14s3 Pvencvenc-0\<power-domain@15 s4Pvdecvdec-0vdec-1vdec-2\+<power-domain@16sPvdec2-0vdec2-1vdec2-2<power-domain@17(s   Pcamcam-0cam-1cam-2cam-3\+<power-domain@18s! Pcam_rawa-0<power-domain@19s" Pcam_rawb-0<power-domain@20s# Pcam_rawc-0<watchdog@10007000mediatek,mt8192-wdtp)syscon@1000c000"mediatek,mt8192-apmixedsyssysconf'timer@10017000,mediatek,mt8192-timermediatek,mt6765-timerps$pwrap@10026000mediatek,mt6873-pwrap` pwraps Pspiwrapn~pmicmediatek,mt6359mt6359codecregulatorsbuck_vs1vs1 5!buck_vgpu11vgpu117 buck_vmodemvmodem*buck_vpuvpu7 buck_vcorevcore  buck_vs2vs2 5jbuck_vpavpa 7,buck_vproc2vproc27L buck_vproc1vproc17L buck_vcore_sshub vcore_sshub7buck_vgpu11_sshub vgpu11_sshub7ldo_vaud18vaud18w@w@ldo_vsim1vsim1/M`ldo_vibrvibrO2Zldo_vrf12vrf12 ldo_vusbvusb--ldo_vsram_proc2 vsram_proc2 Lldo_vio18vio18ldo_vcamiovcamioldo_vcn18vcn18w@w@ldo_vfe28vfe28**xldo_vcn13vcn13  ldo_vcn33_1_bt vcn33_1_bt*5gldo_vcn33_1_wifi vcn33_1_wifi*5gldo_vaux18vaux18w@w@ldo_vsram_others vsram_others ldo_vefusevefuseldo_vxo22vxo22w@!ldo_vrfckvrfck`ldo_vrfck_1vrfckjldo_vbif28vbif28**ldo_vio28vio28*2Zldo_vemcvemc,@ 2Zldo_vemc_1vemc&%2Zldo_vcn33_2_bt vcn33_2_bt*5gldo_vcn33_2_wifi vcn33_2_wifi*5gldo_va12va12O ldo_va09va09 5Oldo_vrf18vrf18Pldo_vsram_md vsram_md *ldo_vufsvufsldo_vm18vm18ldo_vbbckvbbckOldo_vsram_proc1 vsram_proc1 Lldo_vsim2vsim2/M`ldo_vsram_others_sshubvsram_others_sshub mt6359rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt6873-spmi p  pmifspmimsts8(Ppmif_sys_ckpmif_tmr_ckspmimst_clk_muxn~mailbox@10228000mediatek,mt8192-gce"@1sPgce3clock-controller@10720000mediatek,mt8192-scp_adsprf=failserial@11002000*mediatek,mt8192-uartmediatek,mt6577-uart m s Pbaudbus=okayserial@11003000*mediatek,mt8192-uartmediatek,mt6577-uart0n s Pbaudbus =disabledclock-controller@11007000mediatek,mt8192-imp_iic_wrap_cpfspi@1100a000(mediatek,mt8192-spimediatek,mt6765-spi+sMPparent-clksel-clkspi-clk =disabledpwm@1100e000mediatek,mt8183-disp-pwmDs!8Pmainmm =disabledspi@11010000(mediatek,mt8192-spimediatek,mt6765-spi+sM<Pparent-clksel-clkspi-clk =disabledspi@11012000(mediatek,mt8192-spimediatek,mt6765-spi+ sM>Pparent-clksel-clkspi-clk =disabledspi@11013000(mediatek,mt8192-spimediatek,mt6765-spi+0sM?Pparent-clksel-clkspi-clk =disabledspi@11018000(mediatek,mt8192-spimediatek,mt6765-spi+sMLPparent-clksel-clkspi-clk =disabledspi@11019000(mediatek,mt8192-spimediatek,mt6765-spi+sMMPparent-clksel-clkspi-clk =disabledspi@1101d000(mediatek,mt8192-spimediatek,mt6765-spi+sMmPparent-clksel-clkspi-clk =disabledspi@1101e000(mediatek,mt8192-spimediatek,mt6765-spi+sMnPparent-clksel-clkspi-clk =disabledscp@10500000mediatek,mt8192-scp0Prp sramcfgl1tcmsPmain =disabledFusb@11200000'mediatek,mt8192-xhcimediatek,mtk-xhci   >  macippcOachosts%&n"#~]] s7'R$Psys_ckref_ckmcu_ckdma_ckxhci_ckx ( f =disabledsyscon@11210000mediatek,mt8192-audsyssyscon! f+mt8192-afe-pcmmediatek,mt8192-audio) audiosys'\*s+++++++++++ + ++++++++/:H/e0i+g,k;<=>?@ABCD7uPaud_afe_clkaud_dac_clkaud_dac_predis_clkaud_adc_clkaud_adda6_adc_clkaud_apll22m_clkaud_apll24m_clkaud_apll1_tuner_clkaud_apll2_tuner_clkaud_tdm_clkaud_tml_clkaud_nleaud_dac_hires_clkaud_adc_hires_clkaud_adc_hires_tmlaud_adda6_adc_hires_clkaud_3rd_dac_clkaud_3rd_dac_predis_clkaud_3rd_dac_tmlaud_3rd_dac_hires_clkaud_infra_clkaud_infra_26m_clktop_mux_audiotop_mux_audio_inttop_mainpll_d4_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d4top_mux_aud_eng2top_apll2_d4top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s3_m_seltop_i2s4_m_seltop_i2s5_m_seltop_i2s6_m_seltop_i2s7_m_seltop_i2s8_m_seltop_i2s9_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div3top_apll12_div4top_apll12_divbtop_apll12_div5top_apll12_div6top_apll12_div7top_apll12_div8top_apll12_div9top_mux_audio_htop_clk26m_clkpcie@11230000mediatek,mt8192-pciepci#   pcie-mac+0s+'*j^\/Ppl_250mtl_26mtl_96mtl_32kperi_26mtop_133mn)~Q8`,,,,interrupt-controller,spi@11234000mediatek,mt8192-nor#@s:w] Pspisfaxin:~+ =disabledefuse@11c10000%mediatek,mt8192-efusemediatek,efuse+data1@1c0Xcalib@580hi2c@11cb0000mediatek,mt8192-i2c !sss-x Pmaindmaz+ =disabledclock-controller@11cb1000mediatek,mt8192-imp_iic_wrap_ef-i2c@11d00000mediatek,mt8192-i2c !vws.x Pmaindmaz+ =disabledi2c@11d01000mediatek,mt8192-i2c !wxs.x Pmaindmaz+ =disabledi2c@11d02000mediatek,mt8192-i2c  !yys.x Pmaindmaz+ =disabledclock-controller@11d03000mediatek,mt8192-imp_iic_wrap_s0f.i2c@11d20000mediatek,mt8192-i2c !qqs/x Pmaindmaz+ =disabledi2c@11d21000mediatek,mt8192-i2c !qrs/x Pmaindmaz+ =disabledi2c@11d22000mediatek,mt8192-i2c  !sts/x Pmaindmaz+ =disabledclock-controller@11d23000 mediatek,mt8192-imp_iic_wrap_ws0f/i2c@11e00000mediatek,mt8192-i2c !uus0x Pmaindmaz+ =disabledclock-controller@11e01000mediatek,mt8192-imp_iic_wrap_wf0t-phy@11e40000.mediatek,mt8192-tphymediatek,generic-tphy-v2+usb-phy@0sPref%usb-phy@700 sPref&dsi-phy@11e50000mediatek,mt8183-mipi-txs' f mipi_tx0_pll =disabled6i2c@11f00000mediatek,mt8192-i2c !pps1x Pmaindmaz+ =disabledi2c@11f01000mediatek,mt8192-i2c !uvs1x Pmaindmaz+ =disabledclock-controller@11f02000mediatek,mt8192-imp_iic_wrap_n f1clock-controller@11f10000mediatek,mt8192-msdc_topf2mmc@11f60000(mediatek,mt8192-mmcmediatek,mt8183-mmc c8s2 222223Psourcehclksource_cgsys_cgpclk_cgaxi_cgahb_cg =disabledmmc@11f70000(mediatek,mt8192-mmcmediatek,mt8183-mmc g8s2 222223Psourcehclksource_cgsys_cgpclk_cgaxi_cgahb_cg =disabledclock-controller@13fbf000mediatek,mt8192-mfgcfgfsyscon@14000000mediatek,mt8192-mmsyssysconf33!3mutex@14001000mediatek,mt8192-disp-mutexs9* smi@14002000mediatek,mt8192-smi-common  s Papbsmigals0gals1* 4larb@14003000mediatek,mt8192-smi-larb0M^4sPapbsmi* 7larb@14004000mediatek,mt8192-smi-larb@M^4sPapbsmi* 8ovl@14005000mediatek,mt8192-disp-ovlPsk55* !3Povl@14006000mediatek,mt8192-disp-ovl-2l`* sk5"5 !3`rdma@140070004mediatek,mt8192-disp-rdmamediatek,mt8183-disp-rdmapsk5r* !3pcolor@140090006mediatek,mt8192-disp-colormediatek,mt8173-disp-color* s!3ccorr@1400a000mediatek,mt8192-disp-ccorr* s !3aal@1400b0002mediatek,mt8192-disp-aalmediatek,mt8183-disp-aal* s!3gamma@1400c0006mediatek,mt8192-disp-gammamediatek,mt8183-disp-gamma* s !3postmask@1400d000mediatek,mt8192-disp-postmask* s !3dither@1400e0008mediatek,mt8192-disp-dithermediatek,mt8183-disp-dither* s !3dsi@14010000mediatek,mt8183-dsi s 6Penginedigitalhss6dphy*  =disabledportendpointovl@14014000mediatek,mt8192-disp-ovl-2l@ * sk5#5!!3@rdma@140150004mediatek,mt8192-disp-rdmamediatek,mt8183-disp-rdmaP * sk5%r!3Pdpi@14016000mediatek,mt8192-dpi`s!'Ppixelenginepll =disabledm4u@1401d000mediatek,mt8192-m4u<789:;<=>?@ABCDEsPbclk* 5clock-controller@15020000mediatek,mt8192-imgsysflarb@1502e000mediatek,mt8192-smi-larbM ^4sPapbsmi* =clock-controller@15820000mediatek,mt8192-imgsys2flarb@1582e000mediatek,mt8192-smi-larbM ^4sPapbsmi* >larb@1600d000mediatek,mt8192-smi-larbM^4sPapbsmi*;clock-controller@1600f000mediatek,mt8192-vdecsys_socflarb@1602e000mediatek,mt8192-smi-larbM^4sPapbsmi*:clock-controller@1602f000mediatek,mt8192-vdecsysfclock-controller@17000000mediatek,mt8192-vencsysflarb@17010000mediatek,mt8192-smi-larbM^4sPapbsmi*<vcodec@17020000mediatek,mt8192-vcodec-enc Xk555555555555F*s Pvenc-set1n3~Wclock-controller@1a000000mediatek,mt8192-camsysf larb@1a001000mediatek,mt8192-smi-larbM ^4s  Papbsmi*?larb@1a002000mediatek,mt8192-smi-larb M^4s  Papbsmi*@larb@1a00f000mediatek,mt8192-smi-larbM^4s!!Papbsmi*Alarb@1a010000mediatek,mt8192-smi-larbM^4s""Papbsmi*Blarb@1a011000mediatek,mt8192-smi-larbM^4s##Papbsmi*Cclock-controller@1a04f000mediatek,mt8192-camsys_rawaf!clock-controller@1a06f000mediatek,mt8192-camsys_rawbf"clock-controller@1a08f000mediatek,mt8192-camsys_rawcf#clock-controller@1b000000mediatek,mt8192-ipesysflarb@1b00f000mediatek,mt8192-smi-larbM^4sPapbsmi* Elarb@1b10f000mediatek,mt8192-smi-larbM^4sPapbsmi* Dclock-controller@1f000000mediatek,mt8192-mdpsysflarb@1f002000mediatek,mt8192-smi-larb M^4sPapbsmi* 9chosenserial0:921600n8memory@40000000memory@ compatibleinterrupt-parent#address-cells#size-cellsmodelovl0ovl-2l0ovl-2l2rdma0rdma4serial0#clock-cellsclocksclock-divclock-multclock-output-namesphandleclock-frequencydevice_typeregenable-methodcpu-idle-statesnext-level-cacheperformance-domainscapacity-dmips-mhzcpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptsranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-ranges#power-domain-cellsclock-namesmediatek,infracfgassigned-clocksassigned-clock-parentsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#mbox-cellsstatus#pwm-cellsinterrupts-extendedinterrupt-namesphyswakeup-sourcemediatek,syscon-wakeupresetsreset-namesmediatek,apmixedsysmediatek,topckgenpower-domainsbus-rangeinterrupt-map-maskinterrupt-map#phy-cellsmboxesmediatek,gce-client-regmediatek,gce-eventsmediatek,larb-idmediatek,smiiommusmediatek,rdma-fifo-sizephy-namesmediatek,larbs#iommu-cellsmediatek,scpstdout-path