-8(Ihisilicon,hip05-d02 +&7Hisilicon Hip05 D02 Development Boardpsci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cluster2core0D core1D core2D core3D cluster3core0Dcore1Dcore2Dcore3Dcpu@20000Hcpuarm,cortex-a57arm,armv8TXpsciflcpu@20001Hcpuarm,cortex-a57arm,armv8TXpsciflcpu@20002Hcpuarm,cortex-a57arm,armv8TXpsciflcpu@20003Hcpuarm,cortex-a57arm,armv8TXpsciflcpu@20100Hcpuarm,cortex-a57arm,armv8TXpsciflcpu@20101Hcpuarm,cortex-a57arm,armv8TXpsciflcpu@20102Hcpuarm,cortex-a57arm,armv8TXpsciflcpu@20103Hcpuarm,cortex-a57arm,armv8TXpscif l cpu@20200Hcpuarm,cortex-a57arm,armv8TXpscif l cpu@20201Hcpuarm,cortex-a57arm,armv8TXpscif l cpu@20202Hcpuarm,cortex-a57arm,armv8TXpscif l cpu@20203Hcpuarm,cortex-a57arm,armv8TXpscif l cpu@20300Hcpuarm,cortex-a57arm,armv8TXpsciflcpu@20301Hcpuarm,cortex-a57arm,armv8TXpsciflcpu@20302Hcpuarm,cortex-a57arm,armv8TXpsciflcpu@20303Hcpuarm,cortex-a57arm,armv8TXpsciflinterrupt-controller@8d000000 arm,gic-v3t+PT0  flinterrupt-controller@8c000000arm,gic-v3-itsTtimerarm,armv8-timer0   pmuarm,armv8-pmuv3 soc simple-bus+refclk200mhz fixed-clock fluart@80300000snps,dw-apb-uartT0 =  apb_pclk!.okuart@80310000snps,dw-apb-uartT1 >  apb_pclk! .disabledmemory@00000000HmemoryTaliases5/soc/uart@80300000chosen=serial0:115200n8 compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodlinux,phandle#interrupt-cellsrangesinterrupt-controller#redistributor-regionsredistributor-strideinterruptsmsi-controller#clock-cellsclock-frequencyclocksclock-namesreg-shiftreg-io-widthstatusserial0stdout-path