:86p(+68$mediatek,mt8173-evbmediatek,mt8173 +!7MediaTek MT8173 evaluation boardcpus+cpu-mapcluster0core0=core1=cluster1core0=core1=cpu@0Acpuarm,cortex-a53MQpsci_oucpu@1Acpuarm,cortex-a53MQpsci_oucpu@100Acpuarm,cortex-a57MQpsci_oucpu@101Acpuarm,cortex-a57MQpsci_ouidle-states}pscicpu-sleep-0arm,idle-state@oupsci arm,psciXsmcoscillator@0 fixed-clock clk26mo u oscillator@1 fixed-clock }clk32koscillator@2 fixed-clock cpum_cktimerarm,armv8-timer 0/   soc+ simple-bus:clock-controller@10000000mediatek,mt8173-topckgenMo u power-controller@10001000 mediatek,mt8173-infracfgsysconMAo u power-controller@10003000mediatek,mt8173-pericfgsysconM0Ao u syscfg_pctl_a@10005000%mediatek,mt8173-pctl-a-syscfgsysconMPoupinctrl@0x10005000mediatek,mt8173-pinctrlMNcu$/o u i2c0oupins1-.i2c1oupins1}~i2c2oupins1+,i2c3oupins1jki2c4oupins1i2c6oupins1demmc0defaultoupins_cmd_dat$9:;<=>?@Bpins_clkApins_rstDmmc1defaultoupins_cmd_datIJKLNfpins_clkMpins_insertmmc0oupins_cmd_dat$9:;<=>?@Bepins_clkAepins_rstDmmc1oupins_cmd_datIJKLNfpins_clkMfspi0oupins_spiEFGHscpsys@10006000mediatek,mt8173-scpsysM` U X imfgmmvencvenc_lt* ouwatchdog@10007000(mediatek,mt8173-wdtmediatek,mt6589-wdtMppwrap@1000d000mediatek,mt8173-pwrapM3pwrap /= Dpwrap  spiwrapmt6397mediatek,mt6397 / mt6397regulatormediatek,mt6397-regulatorbuck_vpca15 Pbuck_vpca15evpca15t `p0buck_vpca7 Pbuck_vpca7evpca7t `p0sbuck_vsramca15Pbuck_vsramca15 evsramca15t `p0buck_vsramca7Pbuck_vsramca7 evsramca7t `p0buck_vcore Pbuck_vcoreevcoret `p0buck_vgpu Pbuck_vgpuevgput `p0sbuck_vdrm Pbuck_vdrmevdrmtO\0buck_vio18 Pbuck_vio18evio18t 6`0ouldo_vtcxo Pldo_vtcxoevtcxoldo_va28 Pldo_va28eva28ldo_vcama Pldo_vcamaevcamat`*ldo_vio28 Pldo_vio28evio28ldo_vusb Pldo_vusbevusbldo_vmcPldo_vmcevmctw@2Zouldo_vmch Pldo_vmchevmcht-2Zouldo_vemc3v3 Pldo_vemc3v3 evemc_3v3t-2Zouldo_vgp1 Pldo_vgp1evcamdt2Zldo_vgp2 Pldo_vgp2evcamiotB@2Zldo_vgp3 Pldo_vgp3evcamaftO2Zldo_vgp4 Pldo_vgp4evgp4tO2Zldo_vgp5 Pldo_vgp5evgp5tO-ldo_vgp6 Pldo_vgp6evgp6tO2Zldo_vibr Pldo_vibrevibrt 2Zintpol-controller@10200620.mediatek,mt8173-sysirqmediatek,mt6577-sysirq M  ouclock-controller@10209000mediatek,mt8173-apmixedsysM interrupt-controller@10220000 arm,gic-400 @M"" "@ "`  / ouserial@11002000*mediatek,mt8173-uartmediatek,mt6577-uartM  /S $  baudbusokayserial@11003000*mediatek,mt8173-uartmediatek,mt6577-uartM0 /T %  baudbus disabledserial@11004000*mediatek,mt8173-uartmediatek,mt6577-uartM@ /U &  baudbus disabledserial@11005000*mediatek,mt8173-uartmediatek,mt6577-uartMP /V '  baudbus disabledi2c@11007000mediatek,mt8173-i2c Mpp /L   maindmadefault+ disabledi2c@11008000mediatek,mt8173-i2c Mp /M   maindmadefault+okayda9211@68 dlg,da9211MhregulatorsBUCKAeVBUCKAt `0)C#'BUCKBeVBUCKBt `0)-'i2c@11009000mediatek,mt8173-i2c Mp /N   maindmadefault+ disabledspi@1100a000mediatek,mt8173-spi+M /n 4 \ parent-clksel-clkspi-clkokaydefault@i2c@11010000mediatek,mt8173-i2c Mp /O   maindmadefault+ disabledi2c@11011000mediatek,mt8173-i2c Mp /P   maindmadefault+ disabledi2c@11013000mediatek,mt8173-i2c M0p /R #  maindmadefault+ disabledaudio-controller@11220000mediatek,mt8173-afe-pcmM" /TP  d e y  binfra_sys_audio_clktop_pdn_audiotop_pdn_aud_intbusbck0bck1i2s0_mi2s1_mi2s2_mi2s3_mi2s3_bb m nr  mmc@11230000(mediatek,mt8173-mmcmediatek,mt8135-mmcM# /G  _ sourcehclkokaydefaultstate_uhsmmc@11240000(mediatek,mt8173-mmcmediatek,mt8135-mmcM$ /H  R sourcehclkokaydefaultstate_uhs  mmc@11250000(mediatek,mt8173-mmcmediatek,mt8135-mmcM% /I  R sourcehclk disabledmmc@11260000(mediatek,mt8173-mmcmediatek,mt8135-mmcM& /J  u sourcehclk disabledclock-controller@14000000mediatek,mt8173-mmsyssysconMclock-controller@15000000mediatek,mt8173-imgsyssysconMclock-controller@16000000mediatek,mt8173-vdecsyssysconMclock-controller@18000000mediatek,mt8173-vencsyssysconMclock-controller@19000000!mediatek,mt8173-vencltsyssysconMaliases /soc/serial@11002000/soc/serial@11003000/soc/serial@11004000#/soc/serial@11005000memory@40000000AmemoryM@chosen compatibleinterrupt-parent#address-cells#size-cellsmodelcpudevice_typeregenable-methodcpu-idle-stateslinux,phandleentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paramcpu_suspendcpu_offcpu_on#clock-cellsclock-frequencyclock-output-namesinterruptsranges#reset-cellsmediatek,pctl-regmappins-are-numberedgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinmuxbias-disableinput-enablebias-pull-upbias-pull-downdrive-strength#power-domain-cellsclocksclock-namesinfracfgreg-namesresetsreset-namesregulator-compatibleregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-enable-ramp-delaystatusclock-divpinctrl-namespinctrl-0regulator-min-microampregulator-max-microampmediatek,pad-selectpower-domainsassigned-clocksassigned-clock-parentspinctrl-1bus-widthmax-frequencycap-mmc-highspeedvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr25cd-gpiosserial0serial1serial2serial3