b#8[(k[.rockchip,px5-evbrockchip,px5rockchip,rk3368 +7Rockchip PX5 EVBaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff660000Q/i2c@ff140000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/serial@ff180000m/serial@ff190000u/serial@ff690000}/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53pscicpu@1cpuarm,cortex-a53pscicpu@2cpuarm,cortex-a53pscicpu@3cpuarm,cortex-a53psci cpu@100cpuarm,cortex-a53pscicpu@101cpuarm,cortex-a53pscicpu@102cpuarm,cortex-a53pscicpu@103cpuarm,cortex-a53psciamba simple-bus+dma-controller@ff250000arm,pl330arm,primecell%@  apb_pclkdma-controller@ff600000arm,pl330arm,primecell`@  apb_pclk9arm-pmuarm,armv8-pmuv3`pqrstuvw   psci arm,psci-0.2smctimerarm,armv8-timer0   oscillator fixed-clock3n6Cxin24mVdwmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @cр   D r vbiuciuciu-driveciu-sampleq | resetokaydefault Z5Adwmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @cр   E s wbiuciuciu-driveciu-sampleq !| reset disableddwmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc@cр   G u ybiuciuciu-driveciu-sampleq #| resetokay3рN]cdefault  5Asaradc@ff100000rockchip,saradc $q I [saradcapb_pclk| W saradc-apb disabledspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spi A Rspiclkapb_pclk ,default + disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spi B Sspiclkapb_pclk -default + disabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spi C Tspiclkapb_pclk )default  !+ disabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c >+i2c Ndefault "okaytouchscreen@40silead,gsl1680@ # # i2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c ?+i2c Odefault $ disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c @+i2c Pdefault % disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c A+i2c Qdefault & disabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uart3n6 M Ubaudclkapb_pclk 7 disabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uart3n6 N Vbaudclkapb_pclk 8 disabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uart3n6 P Xbaudclkapb_pclk : disabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uart3n6 Q Ybaudclkapb_pclk ;okaythermal-zonescpud'tripscpu_alert0$passive(cpu_alert18passive)cpu_crits criticalcooling-mapsmap0*(0/map1*)0/ gpud'tripsgpu_alert08passive*gpu_crit8 criticalcooling-mapsmap0**0/tsadc@ff280000rockchip,rk3368-tsadc( % H Ztsadcapb_pclk|  tsadc-apbinitdefaultsleep +>,H+Rhsokay'ethernet@ff290000rockchip,rk3368-gmac) macirq-8  f g c ]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac disabledusb@ff500000 generic-ehciP  usbhostokayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2X  otgotg@@ okayi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2ce Li2c <default .+okaypmic@1brockchip,rk808 /default 01'232?2K2W2c2o{222Cxin32krk808-clkout2VregulatorsDCDC_REG1 ``vdd_cpuDCDC_REG2 ``vdd_logDCDC_REG3vcc_ddrDCDC_REG42Z2Zvcc_ioLDO_REG1w@w@ vcc18_flashLDO_REG22Z2Zvcca_33LDO_REG3B@B@vdd_10LDO_REG42Z2Zavdd_33LDO_REG5w@2Z vccio_sdLDO_REG6B@B@ vdd10_lcdLDO_REG7w@w@vcc_18LDO_REG8w@w@ vcc18_lcdSWITCH_REG1vcc_sdSWITCH_REG2 vcc33_lcdi2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cf =+i2c Mdefault 3okayaccelerometer@18 bosch,bma250 4pwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault 5 _pwm disabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault 6 _pwm disabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmh  _pwm disabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmh0default 7 _pwm disabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uarti O Wbaudclkapb_pclk 9default 8 disabledmbox@ff6b0000rockchip,rk3368-mailboxk0 E pclk_mailbox disabledsyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfds<io-domains&rockchip,rk3368-pmu-io-voltage-domain disabledreboot-modesyscon-reboot-mode*1RB=RBKRB [RBclock-controller@ff760000rockchip,rk3368-cruv-Vg syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdw-io-domains"rockchip,rk3368-io-voltage-domain disabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdt p Ookaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer  Bspdif@ff880000rockchip,rk3368-spdif 6 S  mclkhclkt9ytxdefault : disabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s (i2s_clki2s_hclk T t99ytxrx disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s 5i2s_clki2s_hclk R t99ytxrxdefault ; disablediommu@ff900800rockchip,iommu iep_mmu  aclkiface disablediommu@ff914000rockchip,iommu @P isp_mmu  aclkiface disablediommu@ff930300rockchip,iommu vop_mmu  aclkiface disablediommu@ff9a0440rockchip,iommu @@@  hevc_mmu  aclkiface disablediommu@ff9a0800rockchip,iommu  vepu_mmuvdpu_mmu  aclkiface disabledefuse@ffb00000rockchip,rk3368-efuse + q pclk_efusecpu-leakage@17temp-adjust@1finterrupt-controller@ffb71000 arm,gic-400@ @ `   pinctrlrockchip,rk3368-pinctrl-<+gpio0@ff750000rockchip,gpio-banku @ Q/gpio1@ff780000rockchip,gpio-bankx A Rgpio2@ff790000rockchip,gpio-banky B S4gpio3@ff7a0000rockchip,gpio-bankz C T#pcfg-pull-up>pcfg-pull-downpcfg-pull-none=pcfg-pull-none-12ma# ?emmcemmc-clk2=emmc-cmd2>emmc-pwr2>emmc-bus12>emmc-bus4@2>>>>emmc-bus82>>>>>>>>gmacrgmii-pins2===? ? ??? ?======rmii-pins2===? ? ?====i2c0i2c0-xfer 2==.i2c1i2c1-xfer 2==3i2c2i2c2-xfer 2 =="i2c3i2c3-xfer 2==$i2c4i2c4-xfer 2==%i2c5i2c5-xfer 2==&i2si2s-8ch-bus2 = ========;pwm0pwm0-pin2=5pwm1pwm1-pin2=6pwm3pwm3-pin2=7sdio0sdio0-bus12>sdio0-bus4@2>>>>sdio0-cmd2>sdio0-clk2=sdio0-cd2>sdio0-wp2>sdio0-pwr2>sdio0-bkpwr2>sdio0-int2>sdmmcsdmmc-clk2 = sdmmc-cmd2 > sdmmc-cd2 >sdmmc-bus12>sdmmc-bus4@2>>>> spdifspdif-tx2=:spi0spi0-clk2>spi0-cs02>spi0-cs12>spi0-tx2>spi0-rx2>spi1spi1-clk2>spi1-cs02>spi1-cs12>spi1-rx2>spi1-tx2>spi2spi2-clk2 >spi2-cs02 >!spi2-rx2 > spi2-tx2 >tsadcotp-gpio2=+otp-out2=,uart0uart0-xfer 2>=uart0-cts2=uart0-rts2=uart1uart1-xfer 2>=uart1-cts2=uart1-rts2=uart2uart2-xfer 2>=8uart3uart3-xfer 2>=uart3-cts2=uart3-rts2=uart4uart4-xfer 2>=uart4-cts2=uart4-rts2=keyspwr-key2=@pmicpmic-sleep2=1pmic-int2>0chosen@serial4:115200n8memory@0@memorygpio-keys gpio-keysdefault @power / LGPIO PowerRt]vcc-sys-regulatorregulator-fixedvcc_sysLK@LK@2 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2cpudevice_typeregenable-method#cooling-cellsphandlerangesinterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-namesinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyfifo-depthresetsreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delayno-emmcno-sdiosd-uhs-sdr12sd-uhs-sdr25pinctrl-namespinctrl-0rockchip,default-sample-phasevmmc-supplyvqmmc-supplymmc-hs200-1_8vno-sdnon-removable#io-channel-cellspower-gpiostouchscreen-size-xtouchscreen-size-ysilead,max-fingersreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-name#pwm-cells#mbox-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathlabellinux,codewakeup-source