a8z (Ay$rockchip,rk3328-evbrockchip,rk3328 +7Rockchip RK3328 EVBaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53xpscicpu@1}cpuarm,cortex-a53xpscicpu@2}cpuarm,cortex-a53xpscicpu@3}cpuarm,cortex-a53xpsci l2-cache0cacheopp_table0operating-points-v2opp-408000000Q~#@4opp-600000000#F~#@opp-8160000000,B@#@opp-1008000000<#@opp-1200000000G(#@opp-1296000000M?d #@amba simple-bus+@dmac@ff1f0000arm,pl330arm,primecell@G Rapb_pclk^ arm-pmuarm,cortex-a53-pmu0Gdefgi display-subsystemrockchip,display-subsystem| psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0G   xin24m fixed-clockn6xin24m<i2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s G)7Ri2s_clki2s_hclk txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s G*8Ri2s_clki2s_hclk  txrx disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s G+9Ri2s_clki2s_hclk txrx disabledspdif@ff030000rockchip,rk3328-spdif G.: Rmclkhclk txdefault  disabledpdm@ff040000 rockchip,pdm=RRpdm_clkpdm_hclk rxdefaultsleep  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd+2io-domains"rockchip,rk3328-io-voltage-domain disabledgrf-gpiorockchip,rk3328-grf-gpio power-controller!rockchip,rk3328-power-controller+4pd_hevc@6pd_video@5pd_vpu@8Freboot-modesyscon-reboot-mode+2RB>RBLRB \RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart G7&Rbaudclkapb_pclk  txrxdefault hu disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart G8'Rbaudclkapb_pclk  txrxdefault hu disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart G9(Rbaudclkapb_pclk  txrxdefaulthuokayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c G$+7 Ri2cpclkdefault disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c G%+8 Ri2cpclkdefaultokayrk805@18rockchip,rk805 Gxin32krk805-clkout2 default!""""##regulatorsDCDC_REG1 vdd_logic 4 5Iregulator-state-mem[sB@DCDC_REG2vdd_arm 4 5Iregulator-state-mem[s~DCDC_REG3vcc_ddr5Iregulator-state-mem[DCDC_REG4vcc_io2Z2Z5I#regulator-state-mem[s2ZLDO_REG1vcc_18w@w@5Iregulator-state-mem[sw@LDO_REG2 vcc18_emmcw@w@5Iregulator-state-mem[sw@LDO_REG3vdd_10B@B@5Iregulator-state-mem[sB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c G&+9 Ri2cpclkdefault$ disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c G'+: Ri2cpclkdefault% disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi G1+ Rspiclkapb_pclk  txrxdefault&'() disabledwatchdog@ff1a0000 snps,dw-wdt G(pwm@ff1b0000rockchip,rk3328-pwm< Rpwmpclkdefault* disabledpwm@ff1b0010rockchip,rk3328-pwm< Rpwmpclkdefault+ disabledpwm@ff1b0020rockchip,rk3328-pwm < Rpwmpclkdefault, disabledpwm@ff1b0030rockchip,rk3328-pwm0 G2< Rpwmpclkdefault- disabledthermal-zonessoc-thermal.tripstrip-point0ppassivetrip-point1Lpassive/soc-crits criticalcooling-mapsmap0/0  tsadc@ff250000rockchip,rk3328-tsadc% G:$(P$Rtsadcapb_pclkinitdefaultsleep01=0GB Ntsadc-apbZ2g~okay.efuse@ff260000rockchip,rk3328-efuse&P+> Rpclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1a=adc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( GP%Rsaradcapb_pclkGV Nsaradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TGZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 RbuscoreGfiommu@ff330200rockchip,iommu3 G` h265e_mmu Raclkiface disablediommu@ff340800rockchip,iommu4@ Gb vepu_mmuF Raclkiface disabledvideo-codec@ff350000rockchip,rk3328-vpu5 G vdpuF Raclkhclk34iommu@ff350800rockchip,iommu5@ G vpu_mmuF Raclkiface43iommu@ff360480rockchip,iommu 6@6@ GJ rkvdec_mmuB Raclkiface disabledvop@ff370000rockchip,rk3328-vop7> G x;Raclk_vopdclk_vophclk_vopG Naxiahbdclk5 disabledport+ endpoint@06;iommu@ff373f00rockchip,iommu7? G vop_mmu; Raclkiface disabled5hdmi@ff3c0000rockchip,rk3328-dw-hdmi<hG#GFRiahbisfrcec7hdmidefault 89:Z2 disabledportsportendpoint;6codec@ff410000rockchip,rk3328-codecA* RpclkmclkZ2 disabledphy@ff430000rockchip,rk3328-hdmi-phyC GS<yRsysclkrefoclkrefpclk hdmi_phy= cpu-version- disabled7clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconDZ28x=&'(ABDC"\5H4$Ez<<<|(n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2-phy@100rockchip,rk3328-usb2phy<Rphyclk usb480m_phy{E>okay>otg-port-$G;<=otg-bvalidotg-idlinestateokayOhost-port- G> linestateokayPdwmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@ G  =!JNRbiuciuciu-driveciu-sample\gрokayudefault?@ABCdwmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@ G  >"KORbiuciuciu-driveciu-sample\gрokayuDdefault EFGdwmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@ G ?#LPRbiuciuciu-driveciu-sample\gрokayudefault HIJethernet@ff540000rockchip,rk3328-gmacT Gmacirq8dWXZYMRstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macGc NstmmacethZ2 disabledethernet@ff550000rockchip,rk3328-gmacUZ2 Gmacirq8TSSUVIRstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyGbdNstmmacethmac-phyrmiiK disabled Loutpute!ETmdiosnps,dwmac-mdio+phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VGddefaultMN5Kusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X GMRotgGotgOap@ O usb2-phyokayusb@ff5c0000 generic-ehci\ G N> RusbhostutmiPusbokayusb@ff5d0000 generic-ohci] G N> RusbhostutmiPusbokayinterrupt-controller@ff811000 arm,gic-400@ @ `  G pinctrlrockchip,rk3328-pinctrlZ2+@gpio0@ff210000rockchip,gpio-bank! G3 ^gpio1@ff220000rockchip,gpio-bank" G4 ]gpio2@ff230000rockchip,gpio-bank# G5  gpio3@ff240000rockchip,gpio-bank$ G6 pcfg-pull-upSpcfg-pull-down[pcfg-pull-noneQpcfg-pull-none-2maZpcfg-pull-up-2mapcfg-pull-up-4maTpcfg-pull-none-4maWpcfg-pull-down-4mapcfg-pull-none-8maUpcfg-pull-up-8maVpcfg-pull-none-12ma Xpcfg-pull-up-12ma Ypcfg-output-highpcfg-output-lowpcfg-input-highRpcfg-inputi2c0i2c0-xfer  QQi2c1i2c1-xfer  QQi2c2i2c2-xfer   QQ$i2c3i2c3-xfer  QQ%i2c3-gpio  QQhdmi_i2chdmii2c-xfer  QQ9pdm-0pdmm0-clk Q pdmm0-fsync Qpdmm0-sdi0 Qpdmm0-sdi1 Qpdmm0-sdi2 Qpdmm0-sdi3 Qpdmm0-clk-sleep Rpdmm0-sdi0-sleep Rpdmm0-sdi1-sleep Rpdmm0-sdi2-sleep Rpdmm0-sdi3-sleep Rpdmm0-fsync-sleep Rtsadcotp-gpio  Q0otp-out  Q1uart0uart0-xfer   SQuart0-cts  Quart0-rts  Quart0-rts-gpio  Quart1uart1-xfer  SQuart1-cts Quart1-rts Quart1-rts-gpio Quart2-0uart2m0-xfer  SQuart2-1uart2m1-xfer  SQspi0-0spi0m0-clk Sspi0m0-cs0  Sspi0m0-tx  Sspi0m0-rx  Sspi0m0-cs1  Sspi0-1spi0m1-clk Sspi0m1-cs0 Sspi0m1-tx Sspi0m1-rx Sspi0m1-cs1 Sspi0-2spi0m2-clk S&spi0m2-cs0 S)spi0m2-tx S'spi0m2-rx S(i2s1i2s1-mclk Qi2s1-sclk Qi2s1-lrckrx Qi2s1-lrcktx Qi2s1-sdi Qi2s1-sdo Qi2s1-sdio1 Qi2s1-sdio2 Qi2s1-sdio3 Qi2s1-sleep RRRRRRRRRi2s2-0i2s2m0-mclk Qi2s2m0-sclk Qi2s2m0-lrckrx Qi2s2m0-lrcktx Qi2s2m0-sdi Qi2s2m0-sdo Qi2s2m0-sleep` RRRRRRi2s2-1i2s2m1-mclk Qi2s2m1-sclk Qi2sm1-lrckrx Qi2s2m1-lrcktx Qi2s2m1-sdi Qi2s2m1-sdo Qi2s2m1-sleepP RRRRRspdif-0spdifm0-tx Qspdif-1spdifm1-tx Qspdif-2spdifm2-tx Q sdmmc0-0sdmmc0m0-pwren Tsdmmc0m0-gpio Tsdmmc0-1sdmmc0m1-pwren Tsdmmc0m1-gpio T_sdmmc0sdmmc0-clk U?sdmmc0-cmd V@sdmmc0-dectn TAsdmmc0-wrprt Tsdmmc0-bus1 Vsdmmc0-bus4@ VVVVBsdmmc0-gpio TTTTTTTTsdmmc0extsdmmc0ext-clk Wsdmmc0ext-cmd Tsdmmc0ext-wrprt Tsdmmc0ext-dectn Tsdmmc0ext-bus1 Tsdmmc0ext-bus4@ TTTTsdmmc0ext-gpio TTTTTTTTsdmmc1sdmmc1-clk  UGsdmmc1-cmd  VFsdmmc1-pwren Vsdmmc1-wrprt Vsdmmc1-dectn Vsdmmc1-bus1 Vsdmmc1-bus4@ VVVVEsdmmc1-gpio  T TTTTTTTTemmcemmc-clk XHemmc-cmd YIemmc-pwren Qemmc-rstnout Qemmc-bus1 Yemmc-bus4@ YYYYemmc-bus8 YYYYYYYYJpwm0pwm0-pin Q*pwm1pwm1-pin Q+pwm2pwm2-pin Q,pwmirpwmir-pin Q-gmac-1rgmiim1-pins`  U WWUWWW W WU UWWUUU UWUUUUrmiim1-pins ZXZZZZ Z ZX X Q QQQQQgmac2phyfephyled-speed100 Qfephyled-speed10 Qfephyled-duplex Qfephyled-rxm0 Qfephyled-txm0 Qfephyled-linkm0 Qfephyled-rxm1 QMfephyled-txm1 Qfephyled-linkm1 QNtsadc_pintsadc-int  Qtsadc-gpio  Qhdmi_pinhdmi-cec Q8hdmi-hpd [:cif-0dvp-d2d9-m0 QQQQQ Q Q QQQQQcif-1dvp-d2d9-m1 QQQQQQQQQQQQpmicpmic-int-l S!sdio-pwrseqwifi-enable-h Q\chosenserial2:1500000n8dc-12vregulator-fixeddc_12v5I`sdio-pwrseqmmc-pwrseq-simpledefault\ %]Dsdmmc-regulatorregulator-fixed 1^default_vcc_sd2Z2Z6#Cvcc-sysregulator-fixedvcc_sys5ILK@LK@6`"vcc-phy-regulatorregulator-fixedvcc_phy5IL compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellsdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsclock-names#dma-cellsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesdmasdma-names#sound-dai-cellsstatuspinctrl-namespinctrl-0pinctrl-1gpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablephy-modephy-handlephy-supplyclock_in_outassigned-clock-ratephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dma#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathreset-gpiosgpiovin-supply