}8u(u$mediatek,mt8173-evbmediatek,mt8173 +!7MediaTek MT8173 evaluation boardaliases=/soc/ovl@1400c000B/soc/ovl@1400d000G/soc/rdma@1400e000M/soc/rdma@1400f000S/soc/rdma@14010000Y/soc/wdma@14011000_/soc/wdma@14012000e/soc/color@14013000l/soc/color@14014000s/soc/split@14018000z/soc/split@14019000/soc/dpi@1401d000/soc/dsi@1401b000/soc/dsi@1401c000/soc/rdma@14001000/soc/rdma@14002000/soc/rsz@14003000/soc/rsz@14004000/soc/rsz@14005000/soc/wdma@14006000/soc/wrot@14007000/soc/wrot@14008000/soc/serial@11002000/soc/serial@11003000/soc/serial@11004000/soc/serial@11005000opp_table0operating-points-v2 opp-50700000084 xopp-702000000)׫ opp-1001000000; @opp-1105000000A@ehopp-1209000000H@opp-1300000000M|m opp-1508000000YAopp-1703000000e*opp_table1operating-points-v2 opp-50700000084 `opp-702000000)׫ :opp-1001000000; @%opp-1209000000H@@opp-1404000000SW]opp-1612000000`+opp-1807000000kopp-2106000000}*cpus+cpu-mapcluster0core0%core1%cluster1core0%core1%cpu@0)cpuarm,cortex-a5359psciGWf mcpuintermediatey  cpu@1)cpuarm,cortex-a5359psciGWf mcpuintermediatey  cpu@100)cpuarm,cortex-a7259psciGWfmcpuintermediatey   cpu@101)cpuarm,cortex-a7259psciGWfmcpuintermediatey   idle-statespscicpu-sleep-0arm,idle-state@pmu_a53arm,cortex-a53-pmu  pmu_a72arm,cortex-a72-pmu  psci#arm,psci-1.0arm,psci-0.2arm,psci@smc*6>oscillator@0 fixed-clockERbclk26moscillator@1 fixed-clockER}bclk32koscillator@2 fixed-clockERbcpum_ckthermal-zonescpu_thermalutripstrip-point@0 0passivetrip-point@1L0passivecpu_crit@08 0criticalcooling-mapsmap@0 map@1reserved-memory+vpu_dma_mem_regionshared-dma-pool5Ptimerarm,armv8-timer 0    soc+ simple-busclock-controller@10000000mediatek,mt8173-topckgen5Epower-controller@10001000 mediatek,mt8173-infracfgsyscon5E power-controller@10003000mediatek,mt8173-pericfgsyscon50E syscfg_pctl_a@10005000%mediatek,mt8173-pctl-a-syscfgsyscon5Ppinctrl@10005000mediatek,mt8173-pinctrl5-?O[p$ xxx@pins1i2c0pins1-.i2c1pins1}~i2c2 pins1+,i2c3$pins1jki2c4%pins1i2c6&pins1dedisp_pwm0_pins>pins1Wmmc0default'pins_cmd_dat$9:;<=>?@Bpins_clkApins_rstDmmc1default+pins_cmd_datIJKLNfpins_clkMpins_insertmmc0(pins_cmd_dat$9:;<=>?@Bepins_clkAepins_rstDmmc1,pins_cmd_datIJKLNfpins_clkMfusb_iddig_pull_up5pins_iddigusb_iddig_pull_down6pins_iddigspi0!pins_spiEFGHscpsys@10006000mediatek,mt8173-scpsys5`fUXimmfgmmvencvenc_ltwatchdog@10007000(mediatek,mt8173-wdtmediatek,mt6589-wdt5ptimer@10008000,mediatek,mt8173-timermediatek,mt6577-timer5  f xpwrap@1000d000mediatek,mt8173-pwrap5pwrap  pwrapf   mspiwrapmt6397mediatek,mt6397  [pmt6397regulatormediatek,mt6397-regulatorbuck_vpca15  buck_vpca155vpca15D `\pt0 buck_vpca7  buck_vpca75vpca7D `\pt0sbuck_vsramca15 buck_vsramca15 5vsramca15D `\pt0buck_vsramca7 buck_vsramca7 5vsramca7D `\pt0 buck_vcore  buck_vcore5vcoreD `\pt0buck_vgpu  buck_vgpu5vgpuD `\pt0sbuck_vdrm  buck_vdrm5vdrmDO\\t0buck_vio18  buck_vio185vio18D \6`t0*ldo_vtcxo  ldo_vtcxo5vtcxoldo_va28  ldo_va285va28ldo_vcama  ldo_vcama5vcamaD`\*ldo_vio28  ldo_vio285vio28ldo_vusb  ldo_vusb5vusb2ldo_vmc ldo_vmc5vmcDw@\2Z.ldo_vmch  ldo_vmch5vmchD-\2Z-ldo_vemc3v3  ldo_vemc3v3 5vemc_3v3D-\2Z)ldo_vgp1  ldo_vgp15vcamdD\2Zldo_vgp2  ldo_vgp25vcamioDB@\2Zldo_vgp3  ldo_vgp35vcamafDO\2Zldo_vgp4  ldo_vgp45vgp4DO\2Zldo_vgp5  ldo_vgp55vgp5DO\-ldo_vgp6  ldo_vgp65vgp6DO\2Zldo_vibr  ldo_vibr5vibrD \2Zcec@10013000mediatek,mt8173-cec50  f okayvpu@10020000mediatek,mt8173-vpu 5 tcmcfg_reg  fgmmain:intpol-controller@10200620.mediatek,mt8173-sysirqmediatek,mt6577-sysirq[p 5  iommu@10205000mediatek,mt8173-m4u5 P  fmbclk9efuse@10206000mediatek,mt8173-efuse5 `+calib@5285( #clock-controller@10209000mediatek,mt8173-apmixedsys5 Ehdmi-phy@10209100mediatek,mt8173-hdmi-phy5 $fmpll_refbhdmitx_dig_cts E okayAmailbox@10212000mediatek,mt8173-gce5!   fmgcemipi-dphy@10215000mediatek,mt8173-mipi-tx5!Pf bmipi_tx0_pllE  disabled;mipi-dphy@10216000mediatek,mt8173-mipi-tx5!`f bmipi_tx1_pllE  disabled<interrupt-controller@10220000 arm,gic-400p [@5"" "@ "`    auxadc@11001000mediatek,mt8173-auxadc5fmmain""serial@11002000*mediatek,mt8173-uartmediatek,mt6577-uart5   Sf$ mbaudbusokayserial@11003000*mediatek,mt8173-uartmediatek,mt6577-uart50  Tf% mbaudbus disabledserial@11004000*mediatek,mt8173-uartmediatek,mt6577-uart5@  Uf& mbaudbus disabledserial@11005000*mediatek,mt8173-uartmediatek,mt6577-uart5P  Vf' mbaudbus disabledi2c@11007000mediatek,mt8173-i2c 5pp  L4f  mmaindma>defaultL+ disabledi2c@11008000mediatek,mt8173-i2c 5p  M4f  mmaindma>defaultL+okayda9211@68 dlg,da92115hregulatorsBUCKA5VBUCKAD `\0VmC#t' BUCKB5VBUCKBD `\0Vm-t'i2c@11009000mediatek,mt8173-i2c 5p  N4f  mmaindma>defaultL + disabledspi@1100a000mediatek,mt8173-spi+5  nf4\mparent-clksel-clkspi-clkokay>defaultL!thermal@1100b000mediatek,mt8173-thermal5  Ff mthermauxadc"#calibration-dataspi@1100d000mediatek,mt8173-nor5f!rmspisf+ disabledi2c@11010000mediatek,mt8173-i2c 5p  O4f  mmaindma>defaultL$+ disabledi2c@11011000mediatek,mt8173-i2c 5p  P4f  mmaindma>defaultL%+ disabledi2c@11012000mediatek,mt8173-hdmi-ddc  Q5 fmddc-i2ci2c@11013000mediatek,mt8173-i2c 50p  R4f#  mmaindma>defaultL&+ disabledaudio-controller@11220000mediatek,mt8173-afe-pcm5"  Pfdeybminfra_sys_audio_clktop_pdn_audiotop_pdn_aud_intbusbck0bck1i2s0_mi2s1_mi2s2_mi2s3_mi2s3_bmnmmc@11230000mediatek,mt8173-mmc5#  Gf_ msourcehclkokay>defaultstate_uhsL'( *8Jg)*mmc@11240000mediatek,mt8173-mmc5$  HfR msourcehclkokay>defaultstate_uhsL+, * -.mmc@11250000mediatek,mt8173-mmc5%  IfR msourcehclk disabledmmc@11260000mediatek,mt8173-mmc5&  Jfu msourcehclk disabledusb@11271000mediatek,mt8173-mtu3 5'0( macippc  @/01 f^msys_ckref_ck +okay23+42otg:>defaultid_floatid_groundL55H6xhci@11270000mediatek,mt8173-xhci5'mac  s f^msys_ckref_ckokay27usb-phy@11290000mediatek,mt8173-u3phy5)+okayusb-phy@112908005)fmref okay/usb-phy@112909005) fmref okay0usb-phy@112910005)fmref okay1clock-controller@14000000mediatek,mt8173-mmsyssyscon5URׄE8rdma@14001000-mediatek,mt8173-mdp-rdmamediatek,mt8173-mdp5f88g9n|:rdma@14002000mediatek,mt8173-mdp-rdma5 f88g9nrsz@14003000mediatek,mt8173-mdp-rsz50f8rsz@14004000mediatek,mt8173-mdp-rsz5@f8rsz@14005000mediatek,mt8173-mdp-rsz5Pf8wdma@14006000mediatek,mt8173-mdp-wdma5`f8 g9nwrot@14007000mediatek,mt8173-mdp-wrot5pf8 g9nwrot@14008000mediatek,mt8173-mdp-wrot5f8 g9novl@1400c000mediatek,mt8173-disp-ovl5  f8g9novl@1400d000mediatek,mt8173-disp-ovl5  f8g9nrdma@1400e000mediatek,mt8173-disp-rdma5  f8g9nrdma@1400f000mediatek,mt8173-disp-rdma5  f8g9nrdma@14010000mediatek,mt8173-disp-rdma5  f8g9nwdma@14011000mediatek,mt8173-disp-wdma5  f8g9nwdma@14012000mediatek,mt8173-disp-wdma5   f8g9ncolor@14013000mediatek,mt8173-disp-color50  f8color@14014000mediatek,mt8173-disp-color5@  f8aal@14015000mediatek,mt8173-disp-aal5P  f8gamma@14016000mediatek,mt8173-disp-gamma5`  f8merge@14017000mediatek,mt8173-disp-merge5pf8split@14018000mediatek,mt8173-disp-split5f8split@14019000mediatek,mt8173-disp-split5f8ufoe@1401a000mediatek,mt8173-disp-ufoe5  f8dsi@1401b000mediatek,mt8173-dsi5  f8$8%;menginedigitalhs;dphy disableddsi@1401c000mediatek,mt8173-dsi5  f8&8'<menginedigitalhs<dphy disableddpi@1401d000mediatek,mt8173-dpi5  f8(8)mpixelenginepllokayportendpoint=Bpwm@1401e0002mediatek,mt8173-disp-pwmmediatek,mt6595-disp-pwm5f8!8 mmainmmokay>defaultL>pwm@1401f0002mediatek,mt8173-disp-pwmmediatek,mt6595-disp-pwm5f8#8"mmainmm disabledmutex@14020000mediatek,mt8173-disp-mutex5  f8larb@14021000mediatek,mt8173-smi-larb5?f88mapbsmismi@14022000mediatek,mt8173-smi-common5 f88mapbsmi?od@14023000mediatek,mt8173-disp-od50f8hdmi@14025000mediatek,mt8173-hdmi5P   f8,8-8.8/mpixelpllbclkspdif>defaultL@Ahdmi8 sAokayports+port@05endpointB=port@15endpointCHlarb@14027000mediatek,mt8173-smi-larb5p?f8282mapbsmiclock-controller@15000000mediatek,mt8173-imgsyssyscon5EDlarb@15001000mediatek,mt8173-smi-larb5?fDDmapbsmiclock-controller@16000000mediatek,mt8173-vdecsyssyscon5EEvcodec@16000000mediatek,mt8173-vcodec-dec5 0@Phpx  n@g9 9!9%9&9'9"9#9$|:@f >lWMiNZmvcodecpllunivpll_d2clk_cci400_selvdec_selvdecpllvencpllvenc_lt_selvdec_bus_clk_src(ilW N>MRXU/larb@16010000mediatek,mt8173-smi-larb5?fEEmapbsmiclock-controller@18000000mediatek,mt8173-vencsyssyscon5EFlarb@18001000mediatek,mt8173-smi-larb5?fFFmapbsmivcodec@18002000mediatek,mt8173-vcodec-enc 5   ng9`9a9b9c9d9i9j9k9l9m9n999999999|: fPX?i2mvenc_sel_srcvenc_selvenc_lt_sel_srcvenc_lt_selXiP?clock-controller@19000000!mediatek,mt8173-vencltsyssyscon5EGlarb@19001000mediatek,mt8173-smi-larb5?fGGmapbsmimemory@40000000)memory5@chosenconnectorhdmi-connectorhdmi0dportendpointHCextcon_iddiglinux,extcon-usb-gpio 4regulator@0regulator-fixed 5usb_vbusDLK@\LK@ 7regulator@1regulator-fixed5vbusDLK@\LK@  3 compatibleinterrupt-parent#address-cells#size-cellsmodelovl0ovl1rdma0rdma1rdma2wdma0wdma1color0color1split0split1dpi0dsi0dsi1mdp_rdma0mdp_rdma1mdp_rsz0mdp_rsz1mdp_rsz2mdp_wdma0mdp_wrot0mdp_wrot1serial0serial1serial2serial3opp-sharedphandleopp-hzopp-microvoltcpudevice_typeregenable-methodcpu-idle-states#cooling-cellsclocksclock-namesoperating-points-v2proc-supplysram-supplyentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paraminterruptsinterrupt-affinitycpu_suspendcpu_offcpu_on#clock-cellsclock-frequencyclock-output-namespolling-delay-passivepolling-delaythermal-sensorssustainable-powertemperaturehysteresistripcooling-devicecontributionrangesalignmentno-map#reset-cellsmediatek,pctl-regmappins-are-numberedgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinmuxinput-enablebias-pull-downbias-disableoutput-lowbias-pull-updrive-strength#power-domain-cellsinfracfgreg-namesresetsreset-namespower-domainsregulator-compatibleregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-enable-ramp-delaystatusmemory-regionmediatek,larbs#iommu-cellsmediatek,ibiasmediatek,ibias_up#phy-cells#mbox-cells#io-channel-cellsclock-divpinctrl-namespinctrl-0regulator-min-microampregulator-max-microampmediatek,pad-select#thermal-sensor-cellsmediatek,auxadcmediatek,apmixedsysnvmem-cellsnvmem-cell-namesassigned-clocksassigned-clock-parentspinctrl-1bus-widthmax-frequencycap-mmc-highspeedmediatek,hs200-cmd-int-delaymediatek,hs400-cmd-int-delaymediatek,hs400-cmd-resp-sel-risingvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr25cd-gpiosphysmediatek,syscon-wakeupvusb33-supplyvbus-supplyextcondr_modewakeup-sourcepinctrl-2assigned-clock-ratesiommusmediatek,larbmediatek,vpuphy-namesphyremote-endpoint#pwm-cellsmediatek,smimediatek,syscon-hdmilabelid-gpioenable-active-high