N)8J$(I$mediatek,mt2712-evbmediatek,mt2712 +!7MediaTek MT2712 evaluation boardopp_table0operating-points-v2=Hopp00P#WB@opp01P)׫WB@opp02P/D8@WB@opp_table1operating-points-v2=H opp00P#WB@opp01P)׫WB@opp02P/D8@WB@opp03P5w"@WB@opp04P; @WB@cpus+cpu-mapcluster0core0ecore1ecluster1core0ecpu@0icpuarm,cortex-a35uy%cpuintermediate Hcpu@1icpuarm,cortex-a35upsciy%cpuintermediate Hcpu@200icpuarm,cortex-a72upsciy'cpuintermediate   Hidle-statespscicpu-sleep-0arm,idle-statedP H cluster-sleep-0arm,idle-state^P H psci arm,psci-0.2smcdummy26m fixed-clock1AHdummyclk fixed-clock1AHoscillator@0 fixed-clockA1Nclk26mH"oscillator@1 fixed-clockA1Nclk32koscillator@2 fixed-clockA1Nclkfpcoscillator@3 fixed-clockA1c.Nclkaud_ext_i_0oscillator@4 fixed-clockA1 Nclkaud_ext_i_1oscillator@5 fixed-clockA1 @Nclkaud_ext_i_2oscillator@6 fixed-clockA1ÀNclki2si0_mck_ioscillator@7 fixed-clockA1ÀNclki2si1_mck_ioscillator@8 fixed-clockA1ÀNclki2si2_mck_ioscillator@9 fixed-clockA1ÀNclktdmin_mclk_itimerarm,armv8-timer 0a   syscon@10000000 mediatek,mt2712-topckgensysconuAHsyscon@10001000 mediatek,mt2712-infracfgsysconuAHsyscon@10003000mediatek,mt2712-pericfgsysconu0AHsyscfg_pctl_a@10005000%mediatek,mt2712-pctl-a-syscfgsysconuPHpinctrl@10005000mediatek,mt2712-pinctrlul aH3usb0_iddigH!pins_iddig usb1_iddigH)pins_iddigscpsys@10006000mediatek,mt2712-scpsyssysconu`0yeihgmmmfgvencjpgdecaudiovdecHserial@1000f000*mediatek,mt2712-uartmediatek,mt6577-uartu ay baudbus disabledspi@10013000mediatek,mt2712-spi-slaveu0 ayspi  disablediommu@10205000mediatek,mt2712-m4uu P aybclk4Csyscon@10209000"mediatek,mt2712-apmixedsyssysconu Aiommu@1020a000mediatek,mt2712-m4uu  aybclk 4Csyscon@10220000mediatek,mt2712-mcucfgsysconu"AHinterrupt-controller@10220a80.mediatek,mt2712-sysirqmediatek,mt6577-sysirq u" @Hinterrupt-controller@10510000 arm,gic-400 @uQRTV a H adc@11001000mediatek,mt2712-auxadcuymainPokayserial@11002000*mediatek,mt2712-uartmediatek,mt6577-uartu  a[y baudbusokayserial@11003000*mediatek,mt2712-uartmediatek,mt6577-uartu0 a\y baudbus disabledserial@11004000*mediatek,mt2712-uartmediatek,mt6577-uartu@ a]y baudbus disabledserial@11005000*mediatek,mt2712-uartmediatek,mt6577-uartuP a^y baudbus disabledpwm@11006000mediatek,mt2712-pwmu`b aMPyf  1topmainpwm1pwm2pwm3pwm4pwm5pwm6pwm7pwm8 disabledi2c@11007000mediatek,mt2712-i2c up aTmy  maindma+ disabledi2c@11008000mediatek,mt2712-i2c u aUmy  maindma+ disabledi2c@11009000mediatek,mt2712-i2c u aVmy  maindma+ disabledspi@1100a000mediatek,mt2712-spi+u avylparent-clksel-clkspi-clk disablednfi@1100e000mediatek,mt2712-nfcu a`ynfi_clkpad_clkw+ disabledecc@1100f000mediatek,mt2712-eccu a_y nfiecc_clk disabledHi2c@11010000mediatek,mt2712-i2c u aWmy  maindma+ disabledi2c@11011000mediatek,mt2712-i2c u aXmy  maindma+ disabledi2c@11013000mediatek,mt2712-i2c u0 aZmy  maindma+ disabledspi@11015000mediatek,mt2712-spi+uP aylparent-clksel-clkspi-clk disabledspi@11016000mediatek,mt2712-spi+u` aylparent-clksel-clkspi-clk disabledspi@10012000mediatek,mt2712-spi+u  aylparent-clksel-clkspi-clk disabledspi@11018000mediatek,mt2712-spi+u aylparent-clksel-clkspi-clk disabledserial@11019000*mediatek,mt2712-uartmediatek,mt6577-uartu a~y baudbus disabledmmc@11230000mediatek,mt2712-mmcu# aO y *,&sourcehclkbus_clksource_cg disabledmmc@11240000mediatek,mt2712-mmcu$ aPy c'sourcehclksource_cg disabledmmc@11250000mediatek,mt2712-mmcu% aQyc(sourcehclksource_cg disabledusb@11271000#mediatek,mt2712-mtu3mediatek,mtu3 u'0( macippc azynsys_ck +okay otgdefault !xhci@11270000'mediatek,mt2712-xhcimediatek,mtk-xhciu'mac a{ yn"sys_ckref_ckokay#usb-phy@11290000mediatek,mt2712-u3phy+okayusb-phy@11290000u)y"refokayHusb-phy@11298000u)y"refokayHusb-phy@11298700u) y"refokayH*usb@112c1000#mediatek,mt2712-mtu3mediatek,mtu3 u,0- macippc a$%&ynsys_ck +okay'(otgdefault )xhci@112c0000'mediatek,mt2712-xhcimediatek,mtk-xhciu,mac a yn"sys_ckref_ckokayusb-phy@112e0000mediatek,mt2712-u3phy+okayusb-phy@112e0000u.y"refokayH$usb-phy@112e8000u.y"refokayH%usb-phy@112e8700u. y"refokayH&pcie@11700000mediatek,mt2712-pcieipci up/ port0port1+asu y#$ sys_ck0sys_ck1ahb_ck0ahb_ck1*&0pcie-phy0pcie-phy1: pcie@0,0ipci disabledu+D`W++++interrupt-controllerH+pcie@1,0ipci disabledu+D`W,,,,interrupt-controllerH,syscon@13000000mediatek,mt2712-mfgcfgsysconuAsyscon@14000000mediatek,mt2712-mmsyssysconuAH.larb@14021000mediatek,mt2712-smi-larbue-ry..apbsmiHsmi@14022000mediatek,mt2712-smi-commonu y..apbsmiH-larb@14027000mediatek,mt2712-smi-larbupe/ry.,.,apbsmiHlarb@14030000mediatek,mt2712-smi-larbue/ry....apbsmiHsmi@14031000mediatek,mt2712-smi-commonuy.-.-apbsmiH/larb@14032000mediatek,mt2712-smi-larbu e/ry.8.8apbsmiHsyscon@15000000mediatek,mt2712-imgsyssysconuAH0larb@15001000mediatek,mt2712-smi-larbue-ry00apbsmiHsyscon@15010000mediatek,mt2712-bdpsyssysconuAsyscon@16000000mediatek,mt2712-vdecsyssysconuAH1larb@16010000mediatek,mt2712-smi-larbue-ry11apbsmiHsyscon@18000000mediatek,mt2712-vencsyssysconuAH2larb@18001000mediatek,mt2712-smi-larbue-ry22apbsmiHlarb@18002000mediatek,mt2712-smi-larbu e-ry22apbsmiHsyscon@19000000!mediatek,mt2712-jpgdecsyssysconuAaliases/serial@11002000memory@40000000imemoryu@chosenserial0:921600n8fixedregulator@0regulator-fixed vproc_buck0B@B@Hfixedregulator@1regulator-fixed vproc_buck1B@B@H extcon_iddiglinux,extcon-usb-gpio 3 H extcon_iddig1linux,extcon-usb-gpio 3H(regulator@2regulator-fixedp0_vbusLK@LK@ 3 Hregulator@3regulator-fixedp1_vbusLK@LK@ 3H'regulator@4regulator-fixedp2_vbusLK@LK@ 3H#regulator@5regulator-fixedp3_vbusLK@LK@ 3 compatibleinterrupt-parent#address-cells#size-cellsmodelopp-sharedphandleopp-hzopp-microvoltcpudevice_typeregclocksclock-namesproc-supplyoperating-points-v2cpu-idle-statesenable-methodentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paramclock-frequency#clock-cellsclock-output-namesinterruptsmediatek,pctl-regmappins-are-numberedgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinmuxbias-pull-up#power-domain-cellsinfracfgstatusassigned-clocksassigned-clock-parentsmediatek,larbs#iommu-cells#io-channel-cells#pwm-cellsclock-divecc-enginereg-namesphyspower-domainsmediatek,syscon-wakeuprangesvbus-supplyextcondr_modewakeup-sourcemediatek,u3p-dis-mskpinctrl-namespinctrl-0#phy-cellsenable-manual-drdphy-namesbus-rangeinterrupt-map-maskinterrupt-mapmediatek,smimediatek,larb-idserial0stdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltid-gpioenable-active-highregulator-always-on