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xdisabledgpu0Ýèëd1 xdisabledgpu1Ýèëd1 xdisablediommu@7fb00000arm,mmu-401arm,smmu-v1i°__¿Ìß xdisabledx2iommu@7fb10000arm,mmu-401arm,smmu-v1i±cc¿Ìx4iommu@7fb20000arm,mmu-401arm,smmu-v1i²aa¿Ìx7iommu@7fb30000arm,mmu-401arm,smmu-v1i³ee¿Ìßx<dma@7ff00000arm,pl330arm,primecellið* lXYZ[\lmnoH222222222È3 íapb_pclkhdlcd@7ff50000 arm,hdlcdiõ ]4È5ípxlclkportendpoint 6x;hdlcd@7ff60000 arm,hdlcdiö U7È5ípxlclkportendpoint 8x:uart@7ff80000arm,pl011arm,primecelliø SÈ9 íuartclkapb_pclki2c@7ffa0000snps,designware-i2ciú-< hU€8ôÈ hdmi-transmitter@70 nxp,tda998xipportendpoint :x8hdmi-transmitter@71 nxp,tda998xiqportendpoint ;x6ohci@7ffb0000 generic-ohciiû t<È=ehci@7ffc0000 generic-ehciiü u<È=memory-controller@7ffd0000arm,pl354arm,primecelliýVWÈ  íapb_pclkmemory@80000000Amemory i€€€tlx@60000000 simple-bus-<`€‘ ¤¨aliasesM/uart@7ff80000chosenUserial0:115200n8psci arm,psci-0.2asmccpus-<cpu-mapcluster0core0=core1=cluster1core0= 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dma-rangesmodelcompatibleinterrupt-parent#address-cells#size-cells#clock-cellsclock-frequencyclock-output-namesphandle#interrupt-cellsinterrupt-map-maskinterrupt-maparm,hbiarm,vexpress,sitearm,v2m-memory-mapregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-ondebounce-intervalwakeup-sourcelinux,codelabelgpiosregbank-widthstatusinterruptsphy-modereg-io-widthsmsc,irq-active-highsmsc,irq-push-pullclocksvdd33a-supplyvddvario-supplyclock-namesassigned-clocksassigned-clock-parentsoffsetlinux,default-triggerdefault-statemax-frequencyvmmc-supplygpio-controller#gpio-cellsinterrupt-controllerframe-numberinterrupt-names#mbox-cells#iommu-cells#global-interruptsdma-coherentpower-domainsmsi-controllerremote-endpointiommusarm,scatter-gatherreg-namescpudevice_typebus-rangelinux,pci-domainmsi-parentiommu-map-maskiommu-mapmboxesshmemclock-indicesnum-domains#power-domain-cells#thermal-sensor-cellspolling-delaypolling-delay-passivethermal-sensors#dma-cells#dma-channels#dma-requestsi2c-sda-hold-time-nsserial0stdout-pathmethodentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-idle-statescapacity-dmips-mhzdynamic-power-coefficientinterrupt-affinity