d 8^($^,MSI Primo81 tablet!2msi,primo81allwinner,sun6i-a31schosen=framebuffer@002allwinner,simple-framebuffersimple-framebufferDde_be0-lcd0-hdmi@W3/2wz ^disabledframebuffer@102allwinner,simple-framebuffersimple-framebuffer Dde_be0-lcd00W3/wz ^disabledetaliases /soc@01c00000/ethernet@01c30000memorymemory@timer2arm,armv7-timer0   n6cpusallwinner,sun6i-a31cpu@02arm,cortex-a7cpuW aO /O SB@ 2DOUcpu@12arm,cortex-a7cpucpu@22arm,cortex-a7cpucpu@32arm,cortex-a7cputhermal-zonescpu_thermal]scooling-mapsmap0 tripscpu_alert0ppassiveOUcpu_crit criticalpmu%2arm,cortex-a7-pmuarm,cortex-a15-pmu0xyz{clocks=osc24M 2fixed-clockn6OUclk@0 2fixed-clockosc32kOUclk@1 2fixed-clock}x@ mii_phy_txO U clk@2 2fixed-clocksY@ gmac_int_txO U clk@01c200d02allwinner,sun7i-a20-gmac-clkW gmac_txO U display-engine$2allwinner,sun6i-a31s-display-engine  ^disabledsoc@01c00000 2simple-bus=dma-controller@01c020002allwinner,sun6i-a31-dma  2WOUlcd-controller@01c0c0002allwinner,sun6i-a31s-tcon VlcdW/ahbtcon-ch0tcon-ch1tcon0-pixel-clockportsport@0endpoint@0 O.U.port@1lcd-controller@01c0d0002allwinner,sun6i-a31-tcon WlcdW0ahbtcon-ch0tcon-ch1tcon1-pixel-clockportsport@0endpoint@1O)U)port@1mmc@01c0f0002allwinner,sun7i-a20-mmc WOQPahbmmcoutputsampleahb <^okay*default8BNXammc@01c100002allwinner,sun7i-a20-mmc WRTSahbmmcoutputsampleahb = ^disabledmmc@01c110002allwinner,sun7i-a20-mmc WUWVahbmmcoutputsampleahb > ^disabledmmc@01c120002allwinner,sun7i-a20-mmc  WXZYahbmmcoutputsample ahb ? ^disabledusb@01c190002allwinner,sun6i-a31-musbW( Gmmc}usb^okayotgphy@01c194002allwinner,sun6i-a31-usb-phyphy_ctrlpmu1pmu2Wdefusb0_phyusb1_phyusb2_phy!usb0_resetusb1_resetusb2_reset^okayOUusb@01c1a000&2allwinner,sun6i-a31-ehcigeneric-ehci HW)}usb^okayusb@01c1a400&2allwinner,sun6i-a31-ohcigeneric-ohci IW+g}usb ^disabledusb@01c1b000&2allwinner,sun6i-a31-ehcigeneric-ehci JW*}usb ^disabledusb@01c1b400&2allwinner,sun6i-a31-ohcigeneric-ohci KW,h}usb ^disabledusb@01c1c400&2allwinner,sun6i-a31-ohcigeneric-ohci MW-i ^disabledclock@01c200002allwinner,sun6i-a31-ccuW hoscloscOUpinctrl@01c208002allwinner,sun6i-a31s-pinctrl0 W@apbhosclosc,=OUgmac_gmii@0IPA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27NgmacWgmac_mii@0TIPA0PA1PA2PA3PA8PA9PA11PA12PA13PA14PA19PA20PA21PA22PA23PA24PA26PA27Ngmacgmac_rgmii@0FIPA0PA1PA2PA3PA9PA10PA11PA12PA13PA14PA19PA20PA25PA26PA27NgmacW(i2c0@0 IPH14PH15Ni2c0OUi2c1@0 IPH16PH17Ni2c1OUi2c2@0 IPH18PH19Ni2c2OUlcd0_rgb888IPD0PD1PD2PD3PD4PD5PD6PD7PD8PD9PD10PD11PD12PD13PD14PD15PD16PD17PD18PD19PD20PD21PD22PD23PD24PD25PD26PD27Nlcd0mmc0@0IPF0PF1PF2PF3PF4PF5Nmmc0WfOUmmc1@0IPG0PG1PG2PG3PG4PG5Nmmc1Wfmmc2@0IPC6PC7PC8PC9PC10PC11Nmmc2Wfmmc2@13IPC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC24Nmmc2Wfmmc3@13IPC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC24Nmmc3W(fspdif@0IPH28Nspdifuart0@0 IPH20PH21Nuart0gt911_int_pin@0IPA3Ngpio_inOUmma8452_int_pin@0IPA9Ngpio_infOUmmc0_cd_pin@0IPA8Ngpio_infOUtimer@01c20c002allwinner,sun4i-a10-timer <Wwatchdog@01c20ca02allwinner,sun6i-a31-wdt spdif@01c21000s2allwinner,sun6i-a31-spdif W>c+ apbspdifrxtx ^disabledlradc@01c228002allwinner,sun4i-a10-lradc-keys( ^okaybutton@158 Volume Upsl button@349 Volume DownrTrtp@01c250002allwinner,sun6i-a31-tsP OUserial@01c280002snps,dw-apb-uart€ WG3rxtx ^disabledserial@01c284002snps,dw-apb-uart„ WH4rxtx ^disabledserial@01c288002snps,dw-apb-uartˆ WI5rxtx ^disabledserial@01c28c002snps,dw-apb-uartŒ WJ6  rxtx ^disabledserial@01c290002snps,dw-apb-uart WK7  rxtx ^disabledserial@01c294002snps,dw-apb-uart” WL8rxtx ^disabledi2c@01c2ac002allwinner,sun6i-a31-i2c¬ WC/^failed*default8i2c@01c2b0002allwinner,sun6i-a31-i2c° WD0^okay*default8ctp@5d*default8 2goodix,gt911] i2c@01c2b4002allwinner,sun6i-a31-i2c´ WE1^okay*default8accelerometer@1c*default8 2fsl,mma8452 i2c@01c2b8002allwinner,sun6i-a31-i2c¸ WF2 ^disabledethernet@01c300002allwinner,sun7i-a20-gmacT Rmmacirq W! stmmacethallwinner_gmac_tx  stmmaceth 1 ^disabledcrypto-engine@01c1500062allwinner,sun6i-a31-cryptoallwinner,sun4i-a10-cryptoP PW\ahbmodahbcodec@01c22c00s2allwinner,sun6i-a31-codec, W= apbcodec*rxtx ^disabledtimer@01c6000082allwinner,sun6i-a31-hstimerallwinner,sun7i-a20-hstimer03456W#spi@01c680002allwinner,sun6i-a31-spiƀ AW$]ahbmodrxtx ^disabledspi@01c690002allwinner,sun6i-a31-spiƐ BW%^ahbmodrxtx ^disabledspi@01c6a0002allwinner,sun6i-a31-spiƠ CW&_ahbmodrxtx ^disabledspi@01c6b0002allwinner,sun6i-a31-spiư DW'`ahbmodrxtx ^disabledinterrupt-controller@01c81000%2arm,cortex-a7-gicarm,cortex-a15-gic  @ ` ,  OUdisplay-frontend@01e00000%2allwinner,sun6i-a31-display-frontend ]W5|u ahbmodram!O U portsport@1endpoint@0!O*U*endpoint@1"O%U%display-frontend@01e20000%2allwinner,sun6i-a31-display-frontend ^W6}v ahbmodram"O U portsport@1endpoint@0#O+U+endpoint@1$O&U&display-backend@01e40000$2allwinner,sun6i-a31-display-backend `W4{x ahbmodram H{Xportsport@0endpoint@0%O"U"endpoint@1&O$U$port@1endpoint@1'O(U(drc@01e500002allwinner,sun6i-a31-drc [W<r ahbmodram(HXportsport@0endpoint@1(O'U'port@1endpoint@1)OUdisplay-backend@01e60000$2allwinner,sun6i-a31-display-backend _W3zw ahbmodramHzXportsport@0endpoint@0*O!U!endpoint@1+O#U#port@1endpoint@0,O-U-drc@01e700002allwinner,sun6i-a31-drc [W;q ahbmodram'HXportsport@0endpoint@0-O,U,port@1endpoint@0.O U rtc@01f000002allwinner,sun6i-a31-rtcT()interrupt-controller@1f00c002allwinner,sun6i-a31-r-intc,  O6U6prcm@01f014002allwinner,sun6i-a31-prcmar100_clk2allwinner,sun6i-a31-ar100-clkW  ar100O/U/ahb0_clk2fixed-factor-clockmwW/ahb0O0U0apb0_clk2allwinner,sun6i-a31-apb0-clkW0apb0O1U1apb0_gates_clk#2allwinner,sun6i-a31-apb0-gates-clkW1Dapb0_pioapb0_irapb0_timerapb0_p2wiapb0_uartapb0_1wireapb0_i2cO2U2ir_clk2allwinner,sun4i-a10-mod0-clkWirO3U3apb0_rst 2allwinner,sun6i-a31-clock-resetO4U4cpucfg@01f01c002allwinner,sun6i-a31-cpuconfigir@01f020002allwinner,sun5i-a13-ir W23apbir4 % @ ^disabledpinctrl@01f02c002allwinner,sun6i-a31-r-pinctrl,-.W2apbhosclosc4,=ir@0IPL4Ns_irp2wiIPL0PL1Ns_p2wiO5U5i2c@01f034002allwinner,sun6i-a31-p2wi4 'W24*default85^okaypmic@682x-powers,axp221h6,ac-power-supply 2x-powers,axp221-ac-power-supply ^disabledbattery-power-supply%2x-powers,axp221-battery-power-supply^okayregulators dcdc1vcc-3v0--OUdcdc2vdd-gpu `$@dcdc3vdd-cpu `$@OUdcdc4 vdd-sys-dll `$@dcdc5 vcc-dram``dc1swvcc-lcdOUdc5ldo vdd-cpus `$@aldo1aldo1aldo2aldo2aldo3avcc)22ZOUdldo1 vcc-wifi2Z2ZOUdldo2dldo2dldo3 vddio-csi**dldo4dldo4eldo1eldo1eldo2eldo2eldo3vdd-mipi-bridgez$@OUldo_io0ldo_io0 ^disabledldo_io1ldo_io1 ^disabledrtc_ldo--rtc_ldodrivevbus usb0-vbus^okayOUusb_power_supply!2x-powers,axp221-usb-power-supply^okayOUahci-5v2regulator-fixedahci-5vLK@LK@ ^disabledusb0-vbus2regulator-fixed usb0-vbusLK@LK@  ^disabledusb1-vbus2regulator-fixed usb1-vbusLK@LK@ ^disabledusb2-vbus2regulator-fixed usb2-vbusLK@LK@ ^disabledvcc3v02regulator-fixedvcc3v0--vcc3v32regulator-fixedvcc3v32Z2Zvcc5v02regulator-fixedvcc5v0LK@LK@ #address-cells#size-cellsinterrupt-parentmodelcompatiblerangesallwinner,pipelineclocksstatusvcc-lcd-supplyvdd-mipi-bridge-supplyethernet0device_typereginterruptsclock-frequencyarm,cpu-registers-not-fw-configuredenable-methodclock-latencyoperating-points#cooling-cellscooling-min-levelcooling-max-levelcpu-supplylinux,phandlepolling-delay-passivepolling-delaythermal-sensorstripcooling-devicetemperaturehysteresis#clock-cellsclock-output-namesallwinner,pipelinesresets#dma-cellsreset-namesclock-namesremote-endpointpinctrl-namespinctrl-0vmmc-supplybus-widthcd-gpioscd-invertedinterrupt-namesphysphy-namesextcondr_modereg-names#phy-cellsusb0_id_det-gpiousb0_vbus_power-supplyusb0_vbus-supplyusb1_vbus-supply#reset-cellsgpio-controllerinterrupt-controller#interrupt-cells#gpio-cellspinsfunctiondrive-strengthbias-pull-up#sound-dai-cellsdmasdma-namesvref-supplylabellinux,codechannelvoltage#thermal-sensor-cellsreg-shiftreg-io-widthtouchscreen-swapped-x-y#io-channel-cellssnps,pblsnps,fixed-burstsnps,force_sf_dma_modeassigned-clocksassigned-clock-ratesclock-divclock-multx-powers,drive-vbus-enx-powers,dcdc-freqregulator-nameregulator-always-onregulator-min-microvoltregulator-max-microvoltregulator-boot-onenable-active-high