a8\([Warp i.MX7 Board!warp,imx7s-warpfsl,imx7schosenmemory,memory8 aliases%Back D-Jregulator-brcm!regulator-fixedU h. default/ brcm_reg)2ZA2Zm @' 'regulator-bt!regulator-fixeddefault0U h.bt_reg)2ZA2Zsound!simple-audio-card~imx7-sgtl5000i2s11simple-audio-card,cpu2simple-audio-card,codec3J1 1 #address-cells#size-cellsmodelcompatibledevice_typereggpio0gpio1gpio2gpio3gpio4gpio5gpio6i2c0i2c1i2c2i2c3mmc0mmc1mmc2serial0serial1serial2serial3serial4serial5serial6spi0spi1spi2spi3clock-frequencyclock-latencyclocksarm-supplylinux,phandle#clock-cellsclock-output-namesinterrupt-parentrangesclock-namesslave-moderemote-endpointcpuinterrupts#interrupt-cellsinterrupt-controllergpio-controller#gpio-cellsgpio-rangespinctrl-namespinctrl-0fsl,ext-reset-outputstatusfsl,input-selfsl,pinsregulator-nameregulator-min-microvoltregulator-max-microvoltanatop-reg-offsetanatop-vol-bit-shiftanatop-vol-bit-widthanatop-min-bit-valanatop-min-voltageanatop-max-voltageanatop-enable-bitregmapvaluemasklinux,keycodewakeup-sourceassigned-clocksassigned-clock-rates#reset-cells#power-domain-cellspower-supply#pwm-cellsassigned-clock-parentsuart-has-rtscts#sound-dai-cellsdma-namesdmasregulator-boot-onregulator-always-onregulator-ramp-delayVDDA-supplyVDDIO-supplyVDDD-supplyfsl,usbphyfsl,usbmiscphy-clkgate-delay-usdr_modephy_type#index-cellsbus-widthkeep-power-in-suspendno-1-8-vnon-removablevmmc-supplypinctrl-1pinctrl-2fsl,tuning-step#dma-cellsfsl,sdma-ram-script-namefsl,num-tx-queuesfsl,num-rx-queuesinterrupt-namesdma-channelsreg-namesautorepeatlabelgpioslinux,codeenable-active-highgpiostartup-delay-ussimple-audio-card,namesimple-audio-card,formatsimple-audio-card,bitclock-mastersimple-audio-card,frame-mastersound-dai