|8u(uFreescale i.MX7 SabreSD Board!fsl,imx7d-sdbfsl,imx7dchosenmemory,memory8aliases%>usb@30b20000!fsl,imx7d-usbfsl,imx27-usb80 *:; okay<hostusbmisc@30b20200$!fsl,imx7d-usbmiscfsl,imx6q-usbmisc80;;usbphynop2!usb-nop-xceiv \main_clk::ethernet@30bf0000!fsl,imx7d-fecfsl,imx6sx-fec80$def(RR*"\ipgahbptpenet_clk_refenet_out okaydefault=+Hrgmii>pcie@0x33800000!fsl,imx7d-pciesnps,dw-pcie83@O dbiconfig,pci0UO@@ zmsiz{|}r+v\pciepcie_buspcie_physw)+2?@@@ Gpciephyapps okay S9dma-apbh@33000000&!fsl,imx7d-dma-apbhfsl,imx28-dma-apbh83 0    gpmi0gpmi1gpmi2gpmi3]^AAgpmi-nand@33002000!fsl,imx7d-gpmi-nand83 3@@gpmi-nandbch bch\gpmi_iogpmi_bch_apbArx-tx  disabled(etm@3007d000"!arm,coresight-etm3xarm,primecell80k VBJ \apb_pclkportendpointsCspi4 !spi-gpiodefaultD E  E  dE gpio-expander@0!fairchild,74hc5958m99regulator-usb-otg1-vbus!regulator-fixed+usb_otg1_vbus:LK@RLK@ E,,regulator-usb-otg2-vbus!regulator-fixed+usb_otg2_vbus:LK@RLK@ F<<regulator-can2-3v3!regulator-fixed +can2-3v3:2ZR2Z  defaultG$$regulator-vref-1v8!regulator-fixed +vref-1v8:w@Rw@regulator-brcm!regulator-fixed F +brcm_regdefaultH:2ZR2Z @33regulator-lcd-3v3!regulator-fixed+lcd-3v3:2ZR2Z 9JJpanel!innolux,at043tn24I E@JportendpointsK #address-cells#size-cellsmodelcompatibledevice_typereggpio0gpio1gpio2gpio3gpio4gpio5gpio6i2c0i2c1i2c2i2c3mmc0mmc1mmc2serial0serial1serial2serial3serial4serial5serial6spi0spi1spi2spi3clock-frequencyclock-latencyclocksoperating-pointsarm-supplylinux,phandle#clock-cellsclock-output-namesinterrupt-parentrangesclock-namesslave-moderemote-endpointcpuinterrupts#interrupt-cellsinterrupt-controllergpio-controller#gpio-cellsgpio-rangespinctrl-namespinctrl-0fsl,ext-reset-outputstatusfsl,input-selfsl,pinsregulator-nameregulator-min-microvoltregulator-max-microvoltanatop-reg-offsetanatop-vol-bit-shiftanatop-vol-bit-widthanatop-min-bit-valanatop-min-voltageanatop-max-voltageanatop-enable-bitregmapvaluemasklinux,keycodewakeup-source#reset-cells#power-domain-cellspower-supplyvref-supply#pwm-cellscs-gpiosspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,pressure-maxti,x-plate-ohmsassigned-clocksassigned-clock-parents#sound-dai-cellsdma-namesdmasxceiver-supplyregulator-boot-onregulator-always-onregulator-ramp-delaywlf,shared-lrclkuart-has-rtsctsfsl,usbphyfsl,usbmiscphy-clkgate-delay-usvbus-supplyphy_typedr_mode#index-cellsbus-widthcd-gpioswp-gpioskeep-power-in-suspendpinctrl-1pinctrl-2non-removablevmmc-supplyfsl,tuning-stepassigned-clock-rates#dma-cellsfsl,sdma-ram-script-namefsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetphy-reset-gpiosreg-namesnum-lanesinterrupt-namesinterrupt-map-maskinterrupt-mapfsl,max-link-speedpower-domainsresetsreset-namesreset-gpiodma-channelsarm,primecell-periphidgpio-sckgpio-mosinum-chipselectsregisters-numberenable-active-highstartup-delay-usenable-gpios