]8X(2X$mediatek,mt8183-evbmediatek,mt8183 +!7MediaTek MT8183 evaluation boardaliases=/soc/i2c@11007000B/soc/i2c@11011000G/soc/i2c@11009000L/soc/i2c@1100f000Q/soc/i2c@11008000V/soc/i2c@11016000[/soc/i2c@11005000`/soc/i2c@1101a000e/soc/i2c@1101b000j/soc/i2c@11014000o/soc/i2c@11015000u/soc/i2c@11017000{/soc/serial@11002000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53psci Tcpu@1cpuarm,cortex-a53psci Tcpu@2cpuarm,cortex-a53psci Tcpu@3cpuarm,cortex-a53psci Tcpu@100cpuarm,cortex-a73psci cpu@101cpuarm,cortex-a73psci cpu@102cpuarm,cortex-a73psci cpu@103cpuarm,cortex-a73psci  idle-statespscicpu-sleeparm,idle-state.?O  cluster-sleep-0arm,idle-state.?O cluster-sleep-1arm,idle-state.?O pmu-a53arm,cortex-a53-pmu `pmu-a73arm,cortex-a73-pmu `psci arm,psci-1.0smcoscillator fixed-clockkxclk26mtimerarm,armv8-timer @`   soc+ simple-bussoc_data@8000000%mediatek,mt8183-efusemediatek,efuse+ disabledinterrupt-controller@c000000 arm,gic-v3 P   @ A B `  ppi-partitionsinterrupt-partition-0interrupt-partition-1 syscon@c530000mediatek,mt8183-mcucfgsyscon Skinterrupt-controller@c530a80.mediatek,mt8183-sysirqmediatek,mt6577-sysirq  S Psyscon@10000000 mediatek,mt8183-topckgensysconksyscon@10001000 mediatek,mt8183-infracfgsysconksyscon@10003000mediatek,mt8183-pericfgsyscon0k#pinctrl@10005000mediatek,mt8183-pinctrlPDiocfg0iocfg1iocfg2iocfg3iocfg4iocfg5iocfg6iocfg7iocfg8eint  `i2c0pins_i2cRS3i2c1pins_i2cQT3i2c2pins_i2cgh3i2c3pins_i2c233i2c4pins_i2cij3i2c5pins_i2c013spi0pins_spiUVWXOmmc0default$pins_cmd_dat${}~z\ipins_clk|vpins_rstimmc0%pins_cmd_dat${}~z\ iepins_clk| vfpins_ds vfpins_rst immc1default(pins_cmd_dat "!\ipins_clk\vpins_pmummc1)pins_cmd_dat "!\iepins_clkvf\spi1pins_spiOspi2pins_spi^Ospi3pins_spiOspi4pins_spiOspi5 pins_spi Owatchdog@10007000mediatek,mt8183-wdtpsyscon@1000c000"mediatek,mt8183-apmixedsyssysconkpwrap@1000d000mediatek,mt8183-pwrappwrap `) spiwrapmt6358mediatek,mt6358 `mt6358codecmediatek,mt6358-soundmt6358regulatormediatek,mt6358-regulatorbuck_vdram1vdram1 L0#7buck_vcorevcore j#7buck_vpavpa 7P7buck_vproc11vproc11 j#7buck_vproc12vproc12 j#7buck_vgpuvgpu j7buck_vs2vs2 L0#buck_vmodemvmodem j#7buck_vs1vs1B@'{l0#ldo_vdram2vdram2 'w@ ldo_vsim1vsim1/M`ldo_vibrvibrO2Z<ldo_vrf12regulator-fixedvrf12OOxldo_vio18regulator-fixedvio18w@w@ #'ldo_vusbvusb-/M`#ldo_vcamioregulator-fixedvcamiow@w@Eldo_vcamdvcamd w@Eldo_vcn18regulator-fixedvcn18w@w@ldo_vfe28regulator-fixedvfe28**ldo_vsram_proc11 vsram_proc11 j#ldo_vcn28regulator-fixedvcn28**ldo_vsram_others vsram_others j#ldo_vsram_gpu vsram_gpu jldo_vxo22regulator-fixedvxo22!!x#ldo_vefusevefuseldo_vaux18regulator-fixedvaux18w@w@ldo_vmchvmch,@ 2Z<*ldo_vbif28regulator-fixedvbif28**ldo_vsram_proc12 vsram_proc12 j#ldo_vcama1vcama1w@-Eldo_vemcvemc,@ 2Z<&ldo_vio28regulator-fixedvio28**ldo_va12regulator-fixedva12OO#ldo_vrf18regulator-fixedvrf18w@w@xldo_vcn33_bt vcn33_bt2Z5gldo_vcn33_wifi vcn33_wifi2Z5gldo_vcama2vcama2w@-Eldo_vmcvmcw@2Z<+ldo_vldo28vldo28*-ldo_vaud28regulator-fixedvaud28**ldo_vsim2vsim2/M`mt6358rtcmediatek,mt6358-rtcscp@10500000mediatek,mt8183-scp P\ sramcfg `mainO disabledtimer@10017000,mediatek,mt8183-timermediatek,mt6765-timerp `qclk13mmailbox@10238000mediatek,mt8183-gce#@ `]gceauxadc@11001000.mediatek,mt8183-auxadcmediatek,mt8173-auxadc#mainiokayserial@11002000*mediatek,mt8183-uartmediatek,mt6577-uart  `[  baudbusokayserial@11003000*mediatek,mt8183-uartmediatek,mt6577-uart0 `\  baudbus disabledserial@11004000*mediatek,mt8183-uartmediatek,mt6577-uart@ `]  baudbus disabledi2c@11005000mediatek,mt8183-i2c P `WW* maindma{+ disabledi2c@11007000mediatek,mt8183-i2c p `Q * maindma{+okaydefaultxi2c@11008000mediatek,mt8183-i2c  `R *G maindmaarb{+okaydefaultxB@i2c@11009000mediatek,mt8183-i2c  `S *I maindmaarb{+okaydefaultxspi@1100a000mediatek,mt8183-spi+ `x6parent-clksel-clkspi-clkokaydefaulti2c@1100f000mediatek,mt8183-i2c  `T * maindma{+okaydefaultxspi@11010000mediatek,mt8183-spi+ `|68parent-clksel-clkspi-clkokaydefaulti2c@11011000mediatek,mt8183-i2c  `U9* maindma{+okaydefaultxspi@11012000mediatek,mt8183-spi+  `6;parent-clksel-clkspi-clkokaydefaultspi@11013000mediatek,mt8183-spi+0 `6<parent-clksel-clkspi-clkokaydefaulti2c@11014000mediatek,mt8183-i2c @ `H*G maindmaarb{+ disabledi2c@11015000mediatek,mt8183-i2c P `J*I maindmaarb{+ disabledi2c@11016000mediatek,mt8183-i2c ` `VD*E maindmaarb{+okaydefaultxB@i2c@11017000mediatek,mt8183-i2c p `F*E maindmaarb{+ disabledspi@11018000mediatek,mt8183-spi+ `6Kparent-clksel-clkspi-clkokaydefaultspi@11019000mediatek,mt8183-spi+ `6Lparent-clksel-clkspi-clkokaydefault i2c@1101a000mediatek,mt8183-i2c  `Xb* maindma{+ disabledi2c@1101b000mediatek,mt8183-i2c  `Yc* maindma{+ disabledusb@11201000#mediatek,mt8183-mtu3mediatek,mtu3  . > macippc `H!"=Zsys_ckref_ck #+ disabledxhci@11200000'mediatek,mt8183-xhcimediatek,mtk-xhci mac `I=Zsys_ckref_ck disabledsyscon@11220000 mediatek,mt8183-audiosyssyscon"kmmc@11230000mediatek,mt8183-mmc # `Msourcehclksource_cgokaydefaultstate_uhs$% 08>(M&Y'fvUmmc@11240000mediatek,mt8183-mmc $ `N (sourcehclksource_cgokaydefaultstate_uhs() 8M*Y+efuse@11f10000%mediatek,mt8183-efusemediatek,efuseusb-phy@11f40000.mediatek,mt8183-tphymediatek,generic-tphy-v2+okayusb-phy@0refokay!usb-phy@0700 refokay"syscon@13000000mediatek,mt8183-mfgcfgsysconksyscon@14000000mediatek,mt8183-mmsyssysconksyscon@15020000mediatek,mt8183-imgsyssysconksyscon@16000000mediatek,mt8183-vdecsyssysconksyscon@17000000mediatek,mt8183-vencsyssysconksyscon@19000000 mediatek,mt8183-ipu_connsysconksyscon@19010000mediatek,mt8183-ipu_adlsysconksyscon@19180000!mediatek,mt8183-ipu_core0sysconksyscon@19280000!mediatek,mt8183-ipu_core1syscon(ksyscon@1a000000mediatek,mt8183-camsyssysconkmemory@40000000memory@chosenserial0:921600n8reserved-memory+scp_mem_regionshared-dma-poolP+ compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8i2c9i2c10i2c11serial0cpudevice_typeregenable-methodcapacity-dmips-mhzcpu-idle-statesdynamic-power-coefficient#cooling-cellsphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usinterrupts#clock-cellsclock-frequencyclock-output-namesrangesstatus#interrupt-cellsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxmediatek,pull-up-advmediatek,drive-strength-advbias-disableinput-enablebias-pull-upbias-pull-downdrive-strengthoutput-highclocksclock-namesregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-always-onregulator-allowed-modesmemory-region#mbox-cells#io-channel-cellsclock-divpinctrl-namespinctrl-0mediatek,pad-selectphysmediatek,syscon-wakeuppinctrl-1bus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplyassigned-clocksassigned-clock-parentsnon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104cap-sdio-irqno-mmckeep-power-in-suspendenable-sdio-wakeup#phy-cellsmediatek,discthstdout-pathno-map