8y4(x*chipspark,popmetal-rk3288rockchip,rk3288&7PopMetal-RK3288chosenaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000memorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12`@p@ @OOa sB@ ~ ' 9  K 0 $@29EKcpu@501cpuarm,cortex-a12EKcpu@502cpuarm,cortex-a12EKcpu@503cpuarm,cortex-a12EKamba arm,amba-busSdma-controller@ff250000arm,pl330arm,primecell%@Z2 eapb_pclkEKdma-controller@ff600000arm,pl330arm,primecell`@Z2 eapb_pclk qdisableddma-controller@ffb20000arm,pl330arm,primecell@Z2 eapb_pclkEJKJreserved-memorySdma-unusable@fe000000oscillator fixed-clockxn6xin24mE K timerarm,armv7-timer0   xn6timer@ff810000rockchip,rk3288-timer  H 2 a etimerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 2Drvebiuciuciu-driveciu-sample  @qokay /:DdefaultR \hdwmmc@ff0d0000rockchip,rk3288-dw-mshcр 2Eswebiuciuciu-driveciu-sample ! @ qdisableddwmmc@ff0e0000rockchip,rk3288-dw-mshcр 2Ftxebiuciuciu-driveciu-sample "@ qdisableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 2Guyebiuciuciu-driveciu-sample #@qokayu/:DdefaultR\hsaradc@ff100000rockchip,saradc $2I[esaradcapb_pclk qdisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi2ARespiclkapb_pclk  txrx ,DdefaultR qdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi2BSespiclkapb_pclk txrx -DdefaultR  qdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi2CTespiclkapb_pclktxrx .DdefaultR!"#$ qdisabledi2c@ff140000rockchip,rk3288-i2c >ei2c2MDdefaultR%qokayxak8963@0dasahi-kasei,ak8975 &&DdefaultR'l3g4200d@68st,l3g4200d-gyrokmma8452@1d fsl,mma8452&&DdefaultR(i2c@ff150000rockchip,rk3288-i2c ?ei2c2ODdefaultR)qokayi2c@ff160000rockchip,rk3288-i2c @ei2c2PDdefaultR*qokayi2c@ff170000rockchip,rk3288-i2c Aei2c2QDdefaultR+qokayERKRserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 72MUebaudclkapb_pclkDdefaultR,qokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 82NVebaudclkapb_pclkDdefaultR-qokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 92OWebaudclkapb_pclkDdefaultR.qokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :2PXebaudclkapb_pclkDdefaultR/qokayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;2QYebaudclkapb_pclkDdefaultR0qokaythermal-zonesreserve_thermal1cpu_thermald1tripscpu_alert0 ppassiveE2K2cpu_alert1 $passiveE3K3cpu_crit _ criticalcooling-mapsmap0 2 %map1 3 %gpu_thermald1tripsgpu_alert0 ppassiveE4K4gpu_crit _ criticalcooling-mapsmap0 4 %tsadc@ff280000rockchip,rk3288-tsadc( %2HZetsadcapb_pclk 4tsadc-apbDinitdefaultsleepR5@6J5TjsqokayE1K1ethernet@ff290000rockchip,rk3288-gmac) macirq782fgc]Mestmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB 4stmmacethqok8rgmiiinput 9 'B@,<:DdefaultR;S0\usb@ff500000 generic-ehciP 2eusbhoste<jusb qdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 2eotgthoste= jusb2-phy qdisabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 2eotgtotg|@@ e> jusb2-phy qdisabledusb@ff5c0000 generic-ehci\ 2eusbhost qdisabledi2c@ff650000rockchip,rk3288-i2ce <ei2c2LDdefaultR?qokayxpmic@1brockchip,rk808&@DdefaultRABxin32krk808-clkout2CCC CC!C-D9ERC_lregulatorsDCDC_REG1y qpvdd_armEKregulator-state-memDCDC_REG2y Pvdd_gpuregulator-state-memB@DCDC_REG3yvcc_ddrregulator-state-memDCDC_REG4y2Z2Zvcc_ioEKregulator-state-mem2ZLDO_REG1y2Z2Zvcc_lanE8K8regulator-state-mem2ZLDO_REG2y2Z2Z vccio_sdEKregulator-state-memLDO_REG3yB@B@vdd_10regulator-state-memB@LDO_REG4yw@w@ vcc18_lcdregulator-state-memw@LDO_REG5yw@2Zldo5LDO_REG6yB@B@ vdd10_lcdregulator-state-memB@LDO_REG7yw@w@vcc_18EDKDregulator-state-memw@LDO_REG8y2Z2Zvcca_33EYKYregulator-state-mem2ZSWITCH_REG1y vccio_wlE[K[regulator-state-memSWITCH_REG2yvcc_lcdregulator-state-memi2c@ff660000rockchip,rk3288-i2cf =ei2c2NDdefaultREqokaypwm@ff680000rockchip,rk3288-pwmh+DdefaultRF2^epwm qdisabledpwm@ff680010rockchip,rk3288-pwmh+DdefaultRG2^epwm qdisabledpwm@ff680020rockchip,rk3288-pwmh +DdefaultRH2^epwm qdisabledpwm@ff680030rockchip,rk3288-pwmh0+DdefaultRI2^epwm qdisabledbus_intmem@ff700000 mmio-sramp Spsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsEKpower-controller!rockchip,rk3288-power-controller6EMKMpd_vio 2chgfdehilkjpd_hevc 2oppd_video 2pd_gpu 2syscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv7JH,jk$W#gׄeрxhрxhEKsyscon@ff770000rockchip,rk3288-grfsysconwE7K7watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt2p O qdisabledsound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdifl ehclkmclk2TJtx UDdefaultRK7 qdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s UJJtxrxei2s_hclki2s_clk2RDdefaultRL} qdisabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 2}eaclkhclksclkapb_pclk 4crypto-rstqokayvop@ff930000rockchip,rk3288-vop 2eaclk_vopdclk_vophclk_vopM def 4axiahbdclkNqokayportE K endpoint@0OESKSiommu@ff930300rockchip,iommu  vopb_mmuM qokayENKNvop@ff940000rockchip,rk3288-vop 2eaclk_vopdclk_vophclk_vopM  4axiahbdclkPqokayportE K endpoint@0QETKTiommu@ff940300rockchip,iommu  vopl_mmuM qokayEPKPhdmi@ff980000rockchip,rk3288-dw-hdmi7 g2hm eiahbisfrM qokayRportsportendpoint@0SEOKOendpoint@1TEQKQinterrupt-controller@ffc01000 arm,gic-400  @ `   EKefuse@ffb40000rockchip,rockchip-efuse 2q epclk_efusecpu_leakage@17phyrockchip,rk3288-usb-phy7qokayusb-phy0 2]ephyclkE>K>usb-phy142^ephyclkE<K<usb-phy2H2_ephyclkE=K=pinctrlrockchip,rk3288-pinctrl7Sgpio0@ff750000rockchip,gpio-banku Q2@!1E@K@gpio1@ff780000rockchip,gpio-bankx R2A!1gpio2@ff790000rockchip,gpio-banky S2B!1gpio3@ff7a0000rockchip,gpio-bankz T2C!1gpio4@ff7b0000rockchip,gpio-bank{ U2D!1E9K9gpio5@ff7c0000rockchip,gpio-bank| V2E!1gpio6@ff7d0000rockchip,gpio-bank} W2F!1gpio7@ff7e0000rockchip,gpio-bank~ X2G!1E]K]gpio8@ff7f0000rockchip,gpio-bank Y2H!1E&K&hdmihdmi-ddc =UUpcfg-pull-upKEVKVpcfg-pull-downXpcfg-pull-nonegEUKUpcfg-pull-none-12magt EWKWsleepglobal-pwroff=UEBKBddrio-pwroff=Uddr0-retention=Vddr1-retention=Vi2c0i2c0-xfer =UUE?K?i2c1i2c1-xfer =UUE%K%i2c2i2c2-xfer = U UEEKEi2c3i2c3-xfer =UUE)K)i2c4i2c4-xfer =UUE*K*i2c5i2c5-xfer =UUE+K+i2s0i2s0-bus`=UUUUUUELKLsdmmcsdmmc-clk=UE K sdmmc-cmd=VE K sdmmc-cd=VEKsdmmc-bus1=Vsdmmc-bus4@=VVVVEKsdmmc-pwr= UE^K^sdio0sdio0-bus1=Vsdio0-bus4@=VVVVsdio0-cmd=Vsdio0-clk=Usdio0-cd=Vsdio0-wp=Vsdio0-pwr=Vsdio0-bkpwr=Vsdio0-int=Vsdio1sdio1-bus1=Vsdio1-bus4@=VVVVsdio1-cd=Vsdio1-wp=Vsdio1-bkpwr=Vsdio1-int=Vsdio1-cmd=Vsdio1-clk=Usdio1-pwr= Vemmcemmc-clk=UEKemmc-cmd=VEKemmc-pwr= VEKemmc-bus1=Vemmc-bus4@=VVVVemmc-bus8=VVVVVVVVEKspi0spi0-clk= VEKspi0-cs0= VEKspi0-tx=VEKspi0-rx=VEKspi0-cs1=Vspi1spi1-clk= VEKspi1-cs0= VE K spi1-rx=VEKspi1-tx=VEKspi2spi2-cs1=Vspi2-clk=VE!K!spi2-cs0=VE$K$spi2-rx=VE#K#spi2-tx= VE"K"uart0uart0-xfer =VUE,K,uart0-cts=Vuart0-rts=Uuart1uart1-xfer =V UE-K-uart1-cts= Vuart1-rts= Uuart2uart2-xfer =VUE.K.uart3uart3-xfer =VUE/K/uart3-cts= Vuart3-rts= Uuart4uart4-xfer = V UE0K0uart4-cts=Vuart4-rts=Utsadcotp-gpio= UE5K5otp-out= UE6K6pwm0pwm0-pin=UEFKFpwm1pwm1-pin=UEGKGpwm2pwm2-pin=UEHKHpwm3pwm3-pin=UEIKIgmacrgmii-pins=UUUUWWWWUUU WWUUE;K;rmii-pins=UUUUUUUUUUspdifspdif-tx= UEKKKak8963comp-int=VE'K'buttonspwrbtn=VEXKXdvpdvp-pwr=UE`K`irir-int=VE\K\mma8452gsensor-int=VE(K(pmicpmic-int=VEAKAexternal-gmac-clock fixed-clockxsY@ ext_gmacE:K:gpio-keys gpio-keysDdefaultRXbutton@0 @tGPIO Key Powerdio-domains"rockchip,rk3288-io-voltage-domain7YZ8$4@N[ir-receivergpio-ir-receiver @DdefaultR\flash-regulatorregulator-fixed vcc_flashw@w@ZEKsdmmc-regulatorregulator-fixed ] DdefaultR^vcc_sd2Z2ZeZEKvsys-regulatorregulator-fixedvcc_sysLK@LK@yECKCvcc18-dvp-regulatorregulator-fixed vcc18-dvpw@w@Z_EZKZvcc28-dvp-regulatorregulator-fixedv @DdefaultR` vcc28_dvp**yZE_K_ #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsclock-freq-min-maxfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wpnum-slotspinctrl-namespinctrl-0vmmc-supplyvqmmc-supplybroken-cdnon-removable#io-channel-cellsdmasdma-namesst,drdy-int-pinreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmarockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cells#reset-cellsassigned-clock-rates#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-businterrupt-controller#interrupt-cells#phy-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthautorepeatgpioslinux,codelabellinux,input-typegpio-key,wakeupdebounce-intervalaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supplyvin-supplystartup-delay-usenable-active-high