* M32C SERIES ASSEMBLER * SOURCE LIST Fri Jun 27 17:36:30 2014 PAGE 001 SEQ. LOC. OBJ. 0XMSDA .*....*....SOURCE STATEMENT....8....*....9....*....0....*....1....*....2....*....3....*....4....*....5....*....6....*....7....*....8....*....9....*....0 1 2 ;## C Compiler OUTPUT 3 ;## ccom308 Version 5.05.01.000 4 ;## Copyright(C) 1999(2005). Renesas Technology Corp. 5 ;## and Renesas Solutions Corp., All Rights Reserved. 6 ;## Compile Start Time Fri Jun 27 17:36:30 2014 7 8 ;## COMMAND_LINE: ccom308 C:\Users\Administrator\Downloads\ssp_rsk_r8c23_hew-20140307\ssp\target\rsk_m32c87_hew\ssp_workspace\libkernel\Debug\interrupt 9 10 11 ;## Normal Optimize OFF 12 ;## ROM size Optimize OFF 13 ;## Speed Optimize OFF 14 ;## Default ROM is far 15 ;## Default RAM is near 16 17 .GLB __SB__ 18 .SB __SB__ 19 .FB 0 20 21 22 23 24 25 ;## # FUNCTION TOPPERS_assert_abort 26 27 28 29 30 ;## # FUNCTION _syslog_0 31 32 ;## # FUNCTION _syslog_1 33 34 ;## # FUNCTION _syslog_2 35 36 ;## # FUNCTION _syslog_3 37 38 ;## # FUNCTION _syslog_4 39 40 ;## # FUNCTION _syslog_5 41 42 ;## # FUNCTION _syslog_6 43 44 45 ;## # FUNCTION get_flgreg 46 47 ;## # FUNCTION set_flgreg 48 49 ;## # FUNCTION clr_ipl 50 51 ;## # FUNCTION disint 52 53 ;## # FUNCTION enaint 54 55 ;## # FUNCTION jmp_dispatcher 56 57 58 ;## # FUNCTION TOPPERS_disint 59 60 ;## # FUNCTION TOPPERS_enaint 61 62 * M32C SERIES ASSEMBLER * SOURCE LIST Fri Jun 27 17:36:30 2014 PAGE 002 SEQ. LOC. OBJ. 0XMSDA .*....*....SOURCE STATEMENT....8....*....9....*....0....*....1....*....2....*....3....*....4....*....5....*....6....*....7....*....8....*....9....*....0 63 ;## # FUNCTION sil_reb_mem 64 65 ;## # FUNCTION sil_wrb_mem 66 67 ;## # FUNCTION sil_reh_mem 68 69 ;## # FUNCTION sil_wrh_mem 70 71 ;## # FUNCTION sil_reh_bem 72 73 ;## # FUNCTION sil_wrh_bem 74 75 ;## # FUNCTION sil_rew_mem 76 77 ;## # FUNCTION sil_wrw_mem 78 79 ;## # FUNCTION sil_rew_bem 80 81 ;## # FUNCTION sil_wrw_bem 82 83 84 85 86 87 ;## # FUNCTION reset_isp 88 89 90 ;## # FUNCTION sense_context 91 92 ;## # FUNCTION t_lock_cpu 93 94 ;## # FUNCTION i_lock_cpu 95 96 ;## # FUNCTION t_unlock_cpu 97 98 ;## # FUNCTION i_unlock_cpu 99 100 ;## # FUNCTION x_sense_lock 101 102 ;## # FUNCTION x_set_ipm 103 104 ;## # FUNCTION x_get_ipm 105 106 ;## # FUNCTION x_disable_int 107 108 ;## # FUNCTION x_enable_int 109 110 ;## # FUNCTION x_clear_int 111 112 ;## # FUNCTION x_probe_int 113 114 ;## # FUNCTION x_define_inh 115 116 ;## # FUNCTION i_begin_int 117 118 ;## # FUNCTION i_end_int 119 120 ;## # FUNCTION x_define_exc 121 122 ;## # FUNCTION idle_loop 123 124 * M32C SERIES ASSEMBLER * SOURCE LIST Fri Jun 27 17:36:30 2014 PAGE 003 SEQ. LOC. OBJ. 0XMSDA .*....*....SOURCE STATEMENT....8....*....9....*....0....*....1....*....2....*....3....*....4....*....5....*....6....*....7....*....8....*....9....*....0 125 126 ;## # FUNCTION actque_set 127 128 ;## # FUNCTION actque_clear 129 130 ;## # FUNCTION actque_test 131 132 133 134 ;## # FUNCTION _kernel_initialize_interrupt 135 ;## # FRAME AUTO ( i) size 2, offset -4 136 ;## # FRAME AUTO ( inhno) size 2, offset -2 137 ;## # ARG Size(0) Auto Size(4) Context Size(8) 138 139 140 .SECTION program,CODE,ALIGN 141 .align 142 ;## # C_SRC : { 143 .glb __kernel_initialize_interrupt 144 000000 __kernel_initialize_interrupt: 145 000000 EC04 enter #04H 146 000002 8F28 pushm R2,A0 147 ;## # C_SRC : for (i = 0U; i < tnum_inhno; i++) { 148 000004 33FC Z mov.w #0000H,-4[FB] ; i 149 000006 L283: 150 ;## # C_SRC : for (i = 0U; i < tnum_inhno; i++) { 151 000006 B3E6000000rFC cmp.w __kernel_tnum_inhno,-4[FB] ; i 152 00000C CA14 jgeu L287 153 ;## # C_SRC : { 154 00000E 39FC S mov.w -4[FB],R0 ; i 155 000010 F920 Q mov.w #0H,R2 156 000012 C1A3 mov.l R2R0,A0 157 000014 81A2 add.l A0,A0 158 000016 B3CB000000rFE mov.w __kernel_inhinib_inhno[A0],-2[FB] ; inhno 159 00001C E3F1FC Q add.w #0001H,-4[FB] ; i 160 00001F BBE6 B jmp L283 161 000021 L287: 162 ;## # C_SRC : for (i = 0U; i < tnum_intno; i++) { 163 000021 33FC Z mov.w #0000H,-4[FB] ; i 164 000023 L297: 165 ;## # C_SRC : for (i = 0U; i < tnum_intno; i++) { 166 000023 B3E6000000rFC cmp.w __kernel_tnum_intno,-4[FB] ; i 167 000029 CA38 jgeu L301 168 ;## # C_SRC : x_config_int(intinib_intno[i], intinib_intatr[i], intinib_intpri[i]); 169 00002B 39FC S mov.w -4[FB],R0 ; i 170 00002D F920 Q mov.w #0H,R2 171 00002F C9A2 add.l R2R0,R2R0 172 000031 88B100000000r add.l #(0FFFFFFH & __kernel_intinib_intpri),R2R0 173 000037 C1A3 mov.l R2R0,A0 174 000039 C10E push.w [A0] 175 00003B 39FC S mov.w -4[FB],R0 ; i 176 00003D F920 Q mov.w #0H,R2 177 00003F C9A2 add.l R2R0,R2R0 178 000041 88B100000000r add.l #(0FFFFFFH & __kernel_intinib_intatr),R2R0 179 000047 C1A3 mov.l R2R0,A0 180 000049 C10E push.w [A0] 181 00004B 39FC S mov.w -4[FB],R0 ; i 182 00004D F920 Q mov.w #0H,R2 183 00004F C1A3 mov.l R2R0,A0 184 000051 81A2 add.l A0,A0 185 000053 B98B000000r mov.w __kernel_intinib_intno[A0],R0 186 000058 CD000000r A jsr $_kernel_x_config_int * M32C SERIES ASSEMBLER * SOURCE LIST Fri Jun 27 17:36:30 2014 PAGE 004 SEQ. LOC. OBJ. 0XMSDA .*....*....SOURCE STATEMENT....8....*....9....*....0....*....1....*....2....*....3....*....4....*....5....*....6....*....7....*....8....*....9....*....0 187 00005C 53 Q add.l #04H,SP 188 00005D E3F1FC Q add.w #0001H,-4[FB] ; i 189 000060 BBC2 B jmp L297 190 000062 L301: 191 ;## # C_SRC : } 192 000062 8E14 popm R2,A0 193 000064 FC exitd 194 000065 E1: 195 000065 M1: 196 197 198 ;## # FUNCTION dis_int 199 ;## # FRAME AUTO ( intno) size 2, offset -12 200 ;## # FRAME AUTO ( ercd) size 2, offset -10 201 ;## # FRAME AUTO ( locked) size 2, offset -8 202 ;## # FRAME AUTO ( ipl) size 2, offset -6 203 ;## # FRAME AUTO ( ipl) size 2, offset -4 204 ;## # FRAME AUTO ( flg_reg) size 2, offset -2 205 ;## # FRAME AUTO ( intno) size 2, offset -4 206 ;## # REGISTER ARG ( intno) size 2, REGISTER R0 207 ;## # ARG Size(0) Auto Size(12) Context Size(8) 208 209 000065 DE .align 210 ;## # C_SRC : { 211 .glb $dis_int 212 000066 $dis_int: 213 000066 EC0C enter #0cH 214 000068 8F68 pushm R1,R2,A0 215 00006A 31F4 S mov.w R0,-12[FB] ; intno intno 216 ;## # C_SRC : return (intnest > 0); 217 00006C E6D00000r Q cmp.b #00H,__kernel_intnest:16 218 000070 8B04 jleu L321 219 000072 F9A1 Q mov.w #0001H,R0 220 000074 4A S jmp L323 221 000075 L321: 222 000075 03 Z mov.w #0000H,R0 223 000076 L323: 224 ;## # C_SRC : CHECK_TSKCTX(); 225 000076 E990 Q cmp.w #0000H,R0 226 000078 DA07 jeq L315 227 00007A 35F6E7FF S mov.w #0ffe7H,-10[FB] ; ercd 228 00007E BB69 B jmp L397 229 000080 L315: 230 ;## # C_SRC : CHECK_INTNO_DISINT(intno); 231 000080 77F44000 S cmp.w #0040H,-12[FB] ; intno 232 000084 8A07 jltu L327 233 000086 35F6EFFF S mov.w #0ffefH,-10[FB] ; ercd 234 00008A BB5D B jmp L397 235 00008C L327: 236 ;## # C_SRC : return lock_flag; 237 00008C 190000r S mov.w __kernel_lock_flag:16,R0 238 ;## # C_SRC : locked = t_sense_lock(); 239 00008F 31F8 S mov.w R0,-8[FB] ; locked 240 ;## # C_SRC : if (!locked) { 241 000091 9A1B jne L349 242 ;## # C_SRC : Asm(" stc flg, $$[FB]", ipl); 243 ;#### ASM START 244 000093 01D3DAFA stc flg, -6[FB] 245 ;#### ASM END 246 ;## # C_SRC : return ipl; 247 000097 39FA S mov.w -6[FB],R0 ; ipl 248 ;## # C_SRC : { * M32C SERIES ASSEMBLER * SOURCE LIST Fri Jun 27 17:36:30 2014 PAGE 005 SEQ. LOC. OBJ. 0XMSDA .*....*....SOURCE STATEMENT....8....*....9....*....0....*....1....*....2....*....3....*....4....*....5....*....6....*....7....*....8....*....9....*....0 249 000099 883F8F and.b #8fH,R0H 250 00009C 882F50 or.b #50H,R0H 251 00009F 31FC S mov.w R0,-4[FB] ; ipl 252 ;## # C_SRC : uint16_t flg_reg = ipl; 253 0000A1 93FBFCFE mov.w -4[FB],-2[FB] ; ipl flg_reg 254 ;## # C_SRC : Asm(" ldc $$[FB], flg", flg_reg); 255 ;#### ASM START 256 0000A5 01D3CAFE ldc -2[FB], flg 257 ;#### ASM END 258 ;## # C_SRC : lock_flag = true; 259 0000A9 F7E10000r Q mov.w #0001H,__kernel_lock_flag:16 260 0000AD L349: 261 ;## # C_SRC : { 262 0000AD 93FBF4FC mov.w -12[FB],-4[FB] ; intno intno 263 ;## # C_SRC : if(intpri_table[intno] == 0U) 264 0000B1 39FC S mov.w -4[FB],R0 ; intno 265 0000B3 F920 Q mov.w #0H,R2 266 0000B5 C1A3 mov.l R2R0,A0 267 0000B7 81A2 add.l A0,A0 268 0000B9 B98B000000r mov.w __kernel_intpri_table[A0],R0 269 0000BE DA1C jeq L357 270 ;## # C_SRC : *intc_reg[intno] &= ~INTC_LVLMASK; 271 0000C0 39FC S mov.w -4[FB],R0 ; intno 272 0000C2 F920 Q mov.w #0H,R2 273 0000C4 C1A3 mov.l R2R0,A0 274 0000C6 80A102 shlnc.l #2,A0 275 0000C9 B983000000r mov.l __kernel_intc_reg[A0],R2R0 276 0000CE C1A3 mov.l R2R0,A0 277 0000D0 0188CB extz [A0],R1 278 0000D3 88FFF8 and.b #0f8H,R1L 279 0000D6 C03B mov.b R1L,[A0] 280 ;## # C_SRC : ercd = E_OK; 281 0000D8 33F6 Z mov.w #0000H,-10[FB] ; ercd 282 ;## # C_SRC : } 283 0000DA 5B S jmp L359 284 ;## # C_SRC : else { 285 0000DB L357: 286 ;## # C_SRC : ercd = E_OBJ; 287 0000DB 35F6D7FF S mov.w #0ffd7H,-10[FB] ; ercd 288 ;## # C_SRC : } 289 0000DF L359: 290 ;## # C_SRC : if (!locked) { 291 0000DF 39F8 S mov.w -8[FB],R0 ; locked 292 0000E1 9A06 jne L377 293 ;## # C_SRC : lock_flag = false; 294 0000E3 130000r Z mov.w #0000H,__kernel_lock_flag:16 295 ;## # C_SRC : Asm(" ldipl #0"); 296 ;#### ASM START 297 0000E6 D5E8 ldipl #0 298 ;#### ASM END 299 0000E8 L377: 300 0000E8 L397: 301 ;## # C_SRC : return(ercd); 302 0000E8 39F6 S mov.w -10[FB],R0 ; ercd 303 0000EA 8E16 popm R1,R2,A0 304 0000EC FC exitd 305 0000ED E2: 306 0000ED M2: 307 308 309 ;## # FUNCTION ena_int 310 ;## # FRAME AUTO ( intno) size 2, offset -12 * M32C SERIES ASSEMBLER * SOURCE LIST Fri Jun 27 17:36:30 2014 PAGE 006 SEQ. LOC. OBJ. 0XMSDA .*....*....SOURCE STATEMENT....8....*....9....*....0....*....1....*....2....*....3....*....4....*....5....*....6....*....7....*....8....*....9....*....0 311 ;## # FRAME AUTO ( ercd) size 2, offset -10 312 ;## # FRAME AUTO ( locked) size 2, offset -8 313 ;## # FRAME AUTO ( ipl) size 2, offset -6 314 ;## # FRAME AUTO ( ipl) size 2, offset -4 315 ;## # FRAME AUTO ( flg_reg) size 2, offset -2 316 ;## # FRAME AUTO ( intno) size 2, offset -4 317 ;## # REGISTER ARG ( intno) size 2, REGISTER R0 318 ;## # ARG Size(0) Auto Size(12) Context Size(8) 319 320 0000ED DE .align 321 ;## # C_SRC : { 322 .glb $ena_int 323 0000EE $ena_int: 324 0000EE EC0C enter #0cH 325 0000F0 8F78 pushm R1,R2,R3,A0 326 0000F2 31F4 S mov.w R0,-12[FB] ; intno intno 327 ;## # C_SRC : return (intnest > 0); 328 0000F4 E6D00000r Q cmp.b #00H,__kernel_intnest:16 329 0000F8 8B04 jleu L407 330 0000FA F9A1 Q mov.w #0001H,R0 331 0000FC 4A S jmp L409 332 0000FD L407: 333 0000FD 03 Z mov.w #0000H,R0 334 0000FE L409: 335 ;## # C_SRC : CHECK_TSKCTX(); 336 0000FE E990 Q cmp.w #0000H,R0 337 000100 DA08 jeq L401 338 000102 35F6E7FF S mov.w #0ffe7H,-10[FB] ; ercd 339 000106 CE8500 W jmp L483 340 000109 L401: 341 ;## # C_SRC : CHECK_INTNO_DISINT(intno); 342 000109 77F44000 S cmp.w #0040H,-12[FB] ; intno 343 00010D 8A07 jltu L413 344 00010F 35F6EFFF S mov.w #0ffefH,-10[FB] ; ercd 345 000113 BB78 B jmp L483 346 000115 L413: 347 ;## # C_SRC : return lock_flag; 348 000115 190000r S mov.w __kernel_lock_flag:16,R0 349 ;## # C_SRC : locked = t_sense_lock(); 350 000118 31F8 S mov.w R0,-8[FB] ; locked 351 ;## # C_SRC : if (!locked) { 352 00011A 9A1B jne L435 353 ;## # C_SRC : Asm(" stc flg, $$[FB]", ipl); 354 ;#### ASM START 355 00011C 01D3DAFA stc flg, -6[FB] 356 ;#### ASM END 357 ;## # C_SRC : return ipl; 358 000120 39FA S mov.w -6[FB],R0 ; ipl 359 ;## # C_SRC : { 360 000122 883F8F and.b #8fH,R0H 361 000125 882F50 or.b #50H,R0H 362 000128 31FC S mov.w R0,-4[FB] ; ipl 363 ;## # C_SRC : uint16_t flg_reg = ipl; 364 00012A 93FBFCFE mov.w -4[FB],-2[FB] ; ipl flg_reg 365 ;## # C_SRC : Asm(" ldc $$[FB], flg", flg_reg); 366 ;#### ASM START 367 00012E 01D3CAFE ldc -2[FB], flg 368 ;#### ASM END 369 ;## # C_SRC : lock_flag = true; 370 000132 F7E10000r Q mov.w #0001H,__kernel_lock_flag:16 371 000136 L435: 372 ;## # C_SRC : { * M32C SERIES ASSEMBLER * SOURCE LIST Fri Jun 27 17:36:30 2014 PAGE 007 SEQ. LOC. OBJ. 0XMSDA .*....*....SOURCE STATEMENT....8....*....9....*....0....*....1....*....2....*....3....*....4....*....5....*....6....*....7....*....8....*....9....*....0 373 000136 93FBF4FC mov.w -12[FB],-4[FB] ; intno intno 374 ;## # C_SRC : if(intpri_table[intno] == 0u) 375 00013A 39FC S mov.w -4[FB],R0 ; intno 376 00013C F920 Q mov.w #0H,R2 377 00013E C1A3 mov.l R2R0,A0 378 000140 81A2 add.l A0,A0 379 000142 B98B000000r mov.w __kernel_intpri_table[A0],R0 380 000147 DA37 jeq L443 381 ;## # C_SRC : *intc_reg[intno] = (*intc_reg[intno] & ~INTC_LVLMASK) | IPM2ILVL(intpri_table[intno]); 382 000149 39FC S mov.w -4[FB],R0 ; intno 383 00014B F920 Q mov.w #0H,R2 384 00014D C1A3 mov.l R2R0,A0 385 00014F 80A102 shlnc.l #2,A0 386 000152 B183000000r mov.l __kernel_intc_reg[A0],A0 387 000157 01888B extz [A0],R0 388 00015A 4CF8 S and.b #0f8H,R0L 389 00015C 7FFC S mov.w -4[FB],R1 ; intno 390 00015E F960 Q mov.w #0H,R3 391 000160 C1B3 mov.l R3R1,A0 392 000162 81A2 add.l A0,A0 393 000164 B9CB000000r mov.w __kernel_intpri_table[A0],R1 394 000169 A9EF neg.w R1 395 00016B C9B5 or.w R1,R0 396 00016D 7FFC S mov.w -4[FB],R1 ; intno 397 00016F F960 Q mov.w #0H,R3 398 000171 C1B3 mov.l R3R1,A0 399 000173 80A102 shlnc.l #2,A0 400 000176 09C62B000000r mov.b R0L,[__kernel_intc_reg[A0]] 401 ;## # C_SRC : ercd = E_OK; 402 00017C 33F6 Z mov.w #0000H,-10[FB] ; ercd 403 ;## # C_SRC : } 404 00017E 5B S jmp L445 405 ;## # C_SRC : else { 406 00017F L443: 407 ;## # C_SRC : ercd = E_OBJ; 408 00017F 35F6D7FF S mov.w #0ffd7H,-10[FB] ; ercd 409 ;## # C_SRC : } 410 000183 L445: 411 ;## # C_SRC : if (!locked) { 412 000183 39F8 S mov.w -8[FB],R0 ; locked 413 000185 9A06 jne L463 414 ;## # C_SRC : lock_flag = false; 415 000187 130000r Z mov.w #0000H,__kernel_lock_flag:16 416 ;## # C_SRC : Asm(" ldipl #0"); 417 ;#### ASM START 418 00018A D5E8 ldipl #0 419 ;#### ASM END 420 00018C L463: 421 00018C L483: 422 ;## # C_SRC : return(ercd); 423 00018C 39F6 S mov.w -10[FB],R0 ; ercd 424 00018E 8E1E popm R1,R2,R3,A0 425 000190 FC exitd 426 000191 E3: 427 000191 M3: 428 429 .glb $act_tsk 430 .glb $iact_tsk 431 .glb $psnd_dtq 432 .glb $ipsnd_dtq 433 .glb $prcv_dtq 434 .glb $set_flg * M32C SERIES ASSEMBLER * SOURCE LIST Fri Jun 27 17:36:30 2014 PAGE 008 SEQ. LOC. OBJ. 0XMSDA .*....*....SOURCE STATEMENT....8....*....9....*....0....*....1....*....2....*....3....*....4....*....5....*....6....*....7....*....8....*....9....*....0 435 .glb $iset_flg 436 .glb $clr_flg 437 .glb $pol_flg 438 .glb _loc_cpu 439 .glb _iloc_cpu 440 .glb _unl_cpu 441 .glb _iunl_cpu 442 .glb _dis_dsp 443 .glb _ena_dsp 444 .glb _sns_ctx 445 .glb _sns_loc 446 .glb _sns_dsp 447 .glb _sns_dpn 448 .glb _sns_ker 449 .glb _ext_ker 450 .glb $sta_cyc 451 .glb $stp_cyc 452 .glb $sta_alm 453 .glb $stp_alm 454 .glb _get_tim 455 .glb $syslog_wri_log 456 .glb _syslog_printf 457 .glb _syslog_print 458 .glb $syslog_lostmsg 459 .glb _syslog 460 .glb _sil_dly_nse 461 .glb $target_fput_log 462 .glb _sio_initialize 463 .glb $sio_opn_por 464 .glb _sio_cls_por 465 .glb _sio_isr_rcv 466 .glb _sio_isr_snd 467 .glb _sio_snd_chr 468 .glb _sio_rcv_chr 469 .glb _sio_ena_cbr 470 .glb _sio_dis_cbr 471 .glb _sio_irdy_snd 472 .glb _sio_irdy_rcv 473 .glb $sio_pol_snd_chr 474 .glb __kernel_target_initialize 475 .glb __kernel_target_exit 476 .glb __kernel_intnest 477 .glb __kernel_lock_flag 478 .glb __kernel_saved_ipl 479 .glb __kernel_intc_reg 480 .glb __kernel_intpri_table 481 .glb $_kernel_x_config_int 482 .glb __kernel_prc_initialize 483 .glb __kernel_start_dispatch 484 .glb __kernel_call_exit_kernel 485 .glb __kernel_prc_terminate 486 .glb __kernel_initialize_object 487 .glb __kernel_call_inirtn 488 .glb __kernel_call_terrtn 489 .glb _istksz 490 .glb _istk 491 .glb __kernel_kerflg 492 .glb _sta_ker 493 .glb __kernel_exit_kernel 494 .glb __kernel_tmax_tskid 495 .glb __kernel_ready_primap 496 .glb _actque_bitmap * M32C SERIES ASSEMBLER * SOURCE LIST Fri Jun 27 17:36:30 2014 PAGE 009 SEQ. LOC. OBJ. 0XMSDA .*....*....SOURCE STATEMENT....8....*....9....*....0....*....1....*....2....*....3....*....4....*....5....*....6....*....7....*....8....*....9....*....0 497 .glb __kernel_reqflg 498 .glb __kernel_disdsp 499 .glb __kernel_runtsk_curpri 500 .glb __kernel_runtsk_ipri 501 .glb __kernel_initialize_task 502 .glb $_kernel_make_active 503 .glb $_kernel_test_dormant 504 .glb __kernel_search_schedtsk 505 .glb $_kernel_run_task 506 .glb __kernel_dispatcher 507 .glb $_kernel_get_ipri_self 508 .glb $_kernel_get_ipri 509 .glb __kernel_inhinib_inhno 510 .glb __kernel_inhinib_inhatr 511 .glb __kernel_inhinib_entry 512 .glb __kernel_intinib_intno 513 .glb __kernel_intinib_intatr 514 .glb __kernel_intinib_intpri 515 .glb __kernel_tnum_inhno 516 .glb __kernel_tnum_intno 517 ;################################# 518 ;### STATIC DATA INFORMATION ### 519 ;################################# 520 ;################################# 521 ;################################# 522 ;################################# 523 524 .END Information List TOTAL ERROR(S) 00000 TOTAL WARNING(S) 00000 TOTAL LINE(S) 00524 LINES Section List Attr Size Name CODE 00000401(000191H) program