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G2NrS^^_04,00,,?0>IqFc                   @ ``ppp@@@@@@@@@ #(-27FDT_ERR_NOTFOUNDFDT_ERR_EXISTSFDT_ERR_NOSPACEFDT_ERR_BADOFFSETFDT_ERR_BADPATHFDT_ERR_BADPHANDLEFDT_ERR_BADSTATEFDT_ERR_TRUNCATEDFDT_ERR_BADMAGICFDT_ERR_BADVERSIONFDT_ERR_BADSTRUCTUREFDT_ERR_BADLAYOUTFDT_ERR_INTERNALFDT_ERR_BADNCELLSFDT_ERR_BADVALUEFDT_ERR_BADOVERLAYFDT_ERR_NOPHANDLESFDT_ERR_BADFLAGS#address-cells#size-cellsMissing DTB okay/chosen/memory### ERROR ### Please RESET the board ### Could not read count from timer (err %d) %02X%02xWhole Diskhdsdusbdmmcsdxx%s%c%dblk_partitionpartitionFATFAT32** Nested DOS partitions detected, stopping ** ** Can't read partition table on %d:%lu ** bad MBR sector signature 0x%02x%02x %08x-%02xDOS%sEFI%s:%d%s.%sblkidescsiusbsatahostnvmenvmxipefiloadervirtiopvblockblkmaprkmtd#clock-cellsclocksclock-namesEnable %s failed clk %s already disabled Disable %s failed assigned-clock-ratesclkclock-frequencyfixed_rate_raw_clockfixed_clockfixed-clockclock-divclock-multfixed_factor_clockfixed-factor-clock%s: failed to get %s device (parent of %s) %s: %s is not a valid driver name %s: CLK: %s driver bind error [%d]! %s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set ccf_clk_dividerCould not fetch index mux value exceeds LOWORD field ccf_clk_muxgate bit exceeds LOWORD field clk_gateccf_clk_fixed_factorclk_compositedrivers/clk/imx/clk-gate2.cWARNING at %s:%d/%s()! imx_clk_gate2imx_clk_pllv3_genericimx_clk_pllv3_genericv2imx_clk_pllv3_sysimx_clk_pllv3_usbimx_clk_pllv3_avimx_clk_pllv3_enetimx_clk_pfdjh7110_resetapb_bususb_apbusb_utmi_apbstg_axiahbusb_axioscillatorusb_lpmusb_stbusb_125musb_app_125usb_refclkpcie0_axipcie0_apbpcie0_tlpcie1_axipcie1_apbpcie1_tlsec_ahbsec_misc_ahbcpu_rootcpu_corecpu_busperh_rootbus_rootnocstg_busaxi_cfg0ahb0ahb1apb0qspi_ahbqspi_apbpll0_outqspi_ref_srcqspi_refsdio0_ahbsdio1_ahbsdio0_sdcardsdio1_sdcardnoc_bus_stg_axigmac1_ahbgmac1_axigmac_srcgmac1_gtxclkgmac1_gtxcgmac1-rmii-refin-clockgmac1_rmii_rtxgmac1_ptpgmac1_rxgmac1_txgmac1_tx_invgmac0_gtxclkgmac0_ptpgmac0_gtxcuart0_apbuart0_coreuart1_apbuart1_coreuart2_apbuart2_coreuart3_apbuart3_coreuart4_apbuart4_coreuart5_apbuart5_corei2c2_apbi2c5_apbwdt_apbwdt_coreosc_div4apb_funcgmac0_ahbgmac0_axigmac0-rmii-refin-clockgmac0_rmii_rtxgmac0_txgmac0_tx_invotpc_apbjh7110_stg_clkstarfive,jh7110-stgcrgjh7110_aon_clkstarfive,jh7110-aoncrgjh7110_sys_clkstarfive,jh7110-syscrggmac1-rgmii-rxin-clockpll2_outjh7110_clk_pllxpll1_outjh7110_pll_clkstarfive,jh7110-pll/clocks/firmware/reserved-memoryrootroot_drivernoprangessimple_bussimple-bussimple-mfdlittle-endianbig-endiannative-endiansyscon/configgpioinputoutputunusedunknownfuncmiscpagesizepartitionsfixed-partitionsi2c_eepromi2c_eeprom_partitioni2c-eepromatmel,24c01atmel,24c01aatmel,24c02atmel,24c04atmel,24c08atmel,24c08aatmel,24c16aatmel,24mac402atmel,24c32atmel,24c32d-wlatmel,24c64atmel,24c128atmel,24c256atmel,24c512u-boot,i2c-transaction-bytesgeneric_%xi2c_generic_chip_drvu-boot,i2c-offset-leni2c-chipi2c_generici2c-scl-rising-time-nsi2c-scl-falling-time-nsi2c-sda-hold-time-ns%s %s: failed to enable clock udevice *)(NULLTimed out waiting for bus endistimeout in %sabling I2C adapter I2C bus %s has unknown type %#x Timed out. i2c write Failed i2c_designwaresnps,designware-i2cMMC: block number 0x%lx exceeds max(0x%lx) mmc fail to send stop cmd unable to select a mode Select HS400 failed %d Select HS400ES failed %d unable to select a mode : %d Card did not respond to voltage select! : %d No ext_csd found! MMC Device %d not found mmc_blkfifo-depthbus-widthmax-frequencyfifo-modeciubiu%s %s: failed to setup clocks, ret %d snps_dw_mmcsnps,dw-mshc%s:%smmc_spimmc-spi-slotspi_flashjedec_spi_norSF: Failed to set up slave jedec,spi-norspi-flash%s %s: flash operation timed out %s %s: Macronix Quad bit not set enabling reset hack; may not recover from unexpected reboots gpio-controllerpinconfigpinctrl-namespinctrl-%d%s %s: could not find pctldev pinctrl%s%spinsgroupsfunctionstarfive_gpiobias-disablebias-pull-upbias-pull-downdrive-strengthinput-schmitt-enableinput-schmitt-disableinput-enableinput-disableslew-ratejh7110-sys-pinctrlstarfive,jh7110-sys-pinctrlGPIOjh7110-aon-pinctrlstarfive,jh7110-aon-pinctrlRGPIOramUnknown DDR frequency %d unsupport size %lx DDR version: dc2e84f0. starfive_ddrstarfive,jh7110-dmcstdout-pathconsoleNo serial driver foundreg-offsetreg-shiftreg-io-widthns16550_serialns16550ns16550aingenic,jz4780-uartnvidia,tegra20-uartsnps,dw-apb-uart%s %s: Cannot set speed (err=%d) %s %s: Cannot set mode (err=%d) spi-max-frequency%s %s: Invalid cs %d (err=%d) Invalid bus %d (err=%d) %s %s: Invalid chip select %d:%d (err=%d) spi-cpolspi-cphaspi-cs-highspi-3wirespi-half-duplexspi-tx-bus-widthspi-rx-bus-widthspi_generic_drvspi_genericSF: Calibration failed (read) SF: Calibration failed (low range) cdns,is-decoded-cscdns,fifo-depthcdns,fifo-widthcdns,trigger-addresscdns,is-dmaError: subnode with SPI flash config missing! page-sizeblock-sizecdns,tshsl-nscdns,tsd2d-nscdns,tchsh-nscdns,tslch-nscdns,read-delaycadence_spicdns,qspi-norti,am654-ospiQSPI: QSPI is still busy after poll for %d ms. QSPI: flash command execution timeout Indirect write timed out (%i) Indirect read clear completion error (%i) Indirect read completion error (%i) Indirect write clear completion error (%i) Indirect write completion error (%i) timertimebase-frequencyriscv_timer_probe with invalid clock rate 0! riscv_timerriscv,timerriscv_aclint_timerriscv,clint0sifive,clint0riscv,aclint-mtimercpuscpummu-typei-cache-sized-cache-sizeriscv_cpu#reset-cellsresetsreset00 ;;6-Z-Z-Z-Z-Z-Z-^->->-Z-R-0,Z-Z-D->->-Z-Z-Z-Z-Z->->-Z-Z-Z-Z-Z-Z->->-Z-Z-Z-Z-R-Z-Z-6-vvvv2w2w2w2wvJJJ>>=>=>>>=>>=>>>>>>>>ttttttttRelocation of secondary harts has failed, error %d xHhȑ8XhXȓ0PpЖؖ0p(ؖ0ȓ0Pp8Жؖ0p8(ؖ(Жؖ@ȓ0Pp8ЖؖpУأ (8HHPX`hp((88HHXXhhxx((88HHXXhhxx((88HHXXhhxx((88HHXXhhxx((88HHXXhhxx((88HHXXhhxx((88HHXXhhxx((88HHXXhhxx8P`pȩ(@XppqPq@l‹ĉĉTf ʑZ(ĉTr@~Е@.@@Ԗv@ڗ\f`XB Ĝȵ@@hXX  HX 8@PpXDDȷEط E8EPEEF(E8EHEXhEhExE v8j*40>bJ"2h(6 н (@ P `V@?@Ⱦ8`,nX(4d( %$$d':8;j=<T<@@AA~8<`tx2 h'(Z2,'%##8<D(##0(##C0Ht01')`'$ncȫSpqPH(8%:)XX(8.0XЭXhX 8Pرm 0u(6"h(7rp7vV8XPrprx8ƘZxx8e@PƘƘXpZFxV@X(H R пl,: 0@Y`u0z(`;hXp==z: pmhHDp 0sHahZVzu\urx%x%x%'!|~ ;2r* H6vp780GHLثS@YlZ2 aehؿlJ\mq> z$  0 s@ruXz:9 !J8(,starfive,visionfive-2-v1.3bstarfive,jh7110 cpus &= 9+cpu@0sifive,s7riscvAEcpuQ@d@q@~rv64imac_zba_zbbokay9interrupt-controllerriscv,cpu-intc9cpu@1sifive,u74-mcriscvA@@(EcpuQ@d@q ( riscv,sv39~rv64imafdc_zba_zbb(9interrupt-controllerriscv,cpu-intc9cpu@2sifive,u74-mcriscvA@@(EcpuQ@d@q ( riscv,sv39~rv64imafdc_zba_zbb(9interrupt-controllerriscv,cpu-intc9 cpu@3sifive,u74-mcriscvA@@(EcpuQ@d@q ( riscv,sv39~rv64imafdc_zba_zbb(9interrupt-controllerriscv,cpu-intc9 cpu@4sifive,u74-mcriscvA@@(EcpuQ@d@q ( riscv,sv39~rv64imafdc_zba_zbb(9interrupt-controllerriscv,cpu-intc9 oscillator fixed-clock2oscERn69gmac0-rmii-refin-clock fixed-clock2gmac0_rmii_refinER9(soc simple-bus btimer@2000000$starfive,jh7110-clintsifive,clint0APi      9,serial@10000000snps,dw-apb-uartA} baudclkapb_pclk S TokayRn6default9-clock-controller@10230000starfive,jh7110-stgcrgA#E9&i2c@12050000snps,designware-i2cA} ref Q okayR,default98eeprom@50 atmel,24c04AP1spi@13010000cdns,qspi-nor A!@} Zclk_ref > = ?:rst_apbrst_ahbrst_refFV f沀okay9:nor-flash@0jedec,spi-norAfxclock-controller@13020000starfive,jh7110-syscrgA<}oscgmac1_rmii_refingmac1_rgmii_rxini2stx_bclk_exti2stx_lrck_exti2srx_bclk_exti2srx_lrck_exttdm_extmclk_extpll0_outpll1_outpll2_outE    Z  Y9 sys_syscon@13030000-starfive,jh7110-sys-sysconsysconsimple-mfdA9pinctrl@13040000starfive,jh7110-sys-pinctrlA} p okay9 i2c5-09i2c-pinsOP)mmc0-pins9mmc0-pins-rest>>K Zh~mmc1-pins9mmc1-pins07 >K Zh~mmc1-pins1,9L -:P .;T /K )~mmc@16010000 snps,dw-mshcA} [ ]biuciu @:resetK |okayjdefault9;mmc@16020000 snps,dw-mshcA} \ ^biuciu A:resetK >okayjdefault'/ 6 )?9<clock-controller@17000000starfive,jh7110-aoncrgA(}'()  lNoscrtc_oscgmac0_rmii_refingmac0_rgmii_rxinstg_axiahbapb_busgmac0_gtxclkE!9!dmc@15700000starfive,jh7110-dmc Ap & ' ( :axioscapb}  pll1_outRU9CaliasesP/soc/serial@10000000X/soc/spi@13010000]/soc/mmc@16010000b/soc/mmc@16020000g/soc/i2c@12050000chosenlserial0:115200n8memory@40000000EmemoryA@firmwareX/soc/spi@13010000configx compatible#address-cells#size-cellstimebase-frequencyphandleregdevice_typei-cache-block-sizei-cache-setsi-cache-sizenext-level-cacheriscv,isastatusinterrupt-controller#interrupt-cellsd-cache-block-sized-cache-setsd-cache-sized-tlb-setsd-tlb-sizei-tlb-setsi-tlb-sizemmu-typetlb-splitclock-output-names#clock-cellsclock-frequencyrangesinterrupts-extendedclocksclock-namesresetsreg-io-widthreg-shiftreg-offsetcurrent-speedpinctrl-namespinctrl-0#reset-cellsi2c-sda-hold-time-nsi2c-sda-falling-time-nsi2c-scl-falling-time-nspagesizereset-namescdns,fifo-depthcdns,fifo-widthspi-max-frequencycdns,tshsl-nscdns,tsd2d-nscdns,tchsh-nscdns,tslch-nsassigned-clocksassigned-clock-parentsassigned-clock-ratesgpio-controller#gpio-cellspinmuxbias-disableinput-enableinput-schmitt-enablebias-pull-updrive-strengthinput-disableinput-schmitt-disableslew-ratefifo-watermark-aligneddata-addrstarfive,sysregbus-widthcap-mmc-highspeedmmc-ddr-1_8vmmc-hs200-1_8vnon-removablecap-mmc-hw-resetpost-power-on-delay-msno-sdiono-mmccd-gpioscap-sd-highspeedserial0spi0mmc0mmc1i2c5stdout-pathu-boot,spl-payload-offset