8 ( 0ti,omap3-zoom3ti,omap3630ti,omap36xxti,omap3 + 7TI Zoom3chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8lcpux|cpu pmu@54000000arm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busxh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busx + pinmux@30 ti,omap3-padconfpinctrl-singlex08+ 0Npinmux_mmc1_pins0kpinmux_mmc2_pinsPk(*,.02468:pinmux_mmc3_pinskhpinmux_uart1_pins kPNRALpinmux_uart2_pins kDFJHpinmux_uart3_pins kjlnppinmux_wl12xx_gpiok scm_conf@270sysconsimple-busxp0+ p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapxpbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+mcbsp5_mux_fck@68ti,composite-mux-clock|xh mcbsp5_fckti,composite-clock| mcbsp1_mux_fck@4ti,composite-mux-clock|x mcbsp1_fckti,composite-clock| mcbsp2_mux_fck@4ti,composite-mux-clock| xmcbsp2_fckti,composite-clock|mcbsp3_mux_fck@68ti,composite-mux-clock| xhmcbsp3_fckti,composite-clock|mcbsp4_mux_fck@68ti,composite-mux-clock| xhmcbsp4_fckti,composite-clock|clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \+ 0Npinmux_wlan_host_wkup_pinsktarget-module@480a6000ti,sysc-omap2ti,syscxH `DH `HH `Lrevsyscsyss |ick+ H ` aes1@0 ti,omap3-aesxP  txrxtarget-module@480c5000ti,sysc-omap2ti,syscxH PDH PHH PLrevsyscsyss |ick+ H P aes2@0 ti,omap3-aesxPABtxrxprm@48306000 ti,omap3-prmxH0`@ clocks+virt_16_8m_ck fixed-clock Yosc_sys_ck@d40 ti,mux-clock|x @sys_ck@1270ti,divider-clock|0xp;"sys_clkout1@d70ti,gate-clock|x pdpll3_x2_ckfixed-factor-clock|R]dpll3_m2x2_ckfixed-factor-clock|R]!dpll4_x2_ckfixed-factor-clock| R]corex2_fckfixed-factor-clock|!R]#wkup_l4_ickfixed-factor-clock|"R]Rcorex2_d3_fckfixed-factor-clock|#R]corex2_d5_fckfixed-factor-clock|#R]clockdomainscm@48004000 ti,omap3-cmxH@@clocks+dummy_apb_pclk fixed-clock omap_32k_fck fixed-clock Dvirt_12m_ck fixed-clock virt_13m_ck fixed-clock ]@virt_19200000_ck fixed-clock $virt_26000000_ck fixed-clock virt_38_4m_ck fixed-clock Idpll4_ck@d00ti,omap3-dpll-per-j-type-clock|""x D 0 dpll4_m2_ck@d48ti,divider-clock| 0?x H;$dpll4_m2x2_mul_ckfixed-factor-clock|$R]%dpll4_m2x2_ck@d00ti,hsdiv-gate-clock|%x g&omap_96m_alwon_fckfixed-factor-clock|&R]-dpll3_ck@d00ti,omap3-dpll-core-clock|""x @ 0dpll3_m3_ck@1140ti,divider-clock|0x@;'dpll3_m3x2_mul_ckfixed-factor-clock|'R](dpll3_m3x2_ck@d00ti,hsdiv-gate-clock|( x g)emu_core_alwon_ckfixed-factor-clock|)R]fsys_altclk fixed-clock 2mcbsp_clks fixed-clock dpll3_m2_ck@d40ti,divider-clock|0x @;core_ckfixed-factor-clock|R]*dpll1_fck@940ti,divider-clock|*0x @;+dpll1_ck@904ti,omap3-dpll-clock|"+x  $ @ 4dpll1_x2_ckfixed-factor-clock|R],dpll1_x2m2_ck@944ti,divider-clock|,0x D;@cm_96m_fckfixed-factor-clock|-R].omap_96m_fck@d40 ti,mux-clock|."x @Idpll4_m3_ck@e40ti,divider-clock| 0 x@;/dpll4_m3x2_mul_ckfixed-factor-clock|/R]0dpll4_m3x2_ck@d00ti,hsdiv-gate-clock|0x g1omap_54m_fck@d40 ti,mux-clock|12x @<cm_96m_d2_fckfixed-factor-clock|.R]3omap_48m_fck@d40 ti,mux-clock|32x @4omap_12m_fckfixed-factor-clock|4R]Kdpll4_m4_ck@e40ti,divider-clock| 0x@;5dpll4_m4x2_mul_ckti,fixed-factor-clock|5}6dpll4_m4x2_ck@d00ti,gate-clock|6x gdpll4_m5_ck@f40ti,divider-clock| 0?x@;7dpll4_m5x2_mul_ckti,fixed-factor-clock|7}8dpll4_m5x2_ck@d00ti,hsdiv-gate-clock|8x gndpll4_m6_ck@1140ti,divider-clock| 0?x@;9dpll4_m6x2_mul_ckfixed-factor-clock|9R]:dpll4_m6x2_ck@d00ti,hsdiv-gate-clock|:x g;emu_per_alwon_ckfixed-factor-clock|;R]gclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock|*x p=clkout2_src_mux_ck@d70ti,composite-mux-clock|*".<x p>clkout2_src_ckti,composite-clock|=>?sys_clkout2@d70ti,divider-clock|?0@x pmpu_ckfixed-factor-clock|@R]Aarm_fck@924ti,divider-clock|Ax $0emu_mpu_alwon_ckfixed-factor-clock|AR]hl3_ick@a40ti,divider-clock|*0x @;Bl4_ick@a40ti,divider-clock|B0x @;Crm_ick@c40ti,divider-clock|C0x @;gpt10_gate_fck@a00ti,composite-gate-clock|" x Egpt10_mux_fck@a40ti,composite-mux-clock|D"x @Fgpt10_fckti,composite-clock|EFgpt11_gate_fck@a00ti,composite-gate-clock|" x Ggpt11_mux_fck@a40ti,composite-mux-clock|D"x @Hgpt11_fckti,composite-clock|GHcore_96m_fckfixed-factor-clock|IR]mmchs2_fck@a00ti,wait-gate-clock|x mmchs1_fck@a00ti,wait-gate-clock|x i2c3_fck@a00ti,wait-gate-clock|x i2c2_fck@a00ti,wait-gate-clock|x i2c1_fck@a00ti,wait-gate-clock|x mcbsp5_gate_fck@a00ti,composite-gate-clock| x  mcbsp1_gate_fck@a00ti,composite-gate-clock| x  core_48m_fckfixed-factor-clock|4R]Jmcspi4_fck@a00ti,wait-gate-clock|Jx mcspi3_fck@a00ti,wait-gate-clock|Jx mcspi2_fck@a00ti,wait-gate-clock|Jx mcspi1_fck@a00ti,wait-gate-clock|Jx uart2_fck@a00ti,wait-gate-clock|Jx uart1_fck@a00ti,wait-gate-clock|Jx  core_12m_fckfixed-factor-clock|KR]Lhdq_fck@a00ti,wait-gate-clock|Lx core_l3_ickfixed-factor-clock|BR]Msdrc_ick@a10ti,wait-gate-clock|Mx gpmc_fckfixed-factor-clock|MR]core_l4_ickfixed-factor-clock|CR]Nmmchs2_ick@a10ti,omap3-interface-clock|Nx mmchs1_ick@a10ti,omap3-interface-clock|Nx hdq_ick@a10ti,omap3-interface-clock|Nx mcspi4_ick@a10ti,omap3-interface-clock|Nx mcspi3_ick@a10ti,omap3-interface-clock|Nx mcspi2_ick@a10ti,omap3-interface-clock|Nx mcspi1_ick@a10ti,omap3-interface-clock|Nx i2c3_ick@a10ti,omap3-interface-clock|Nx i2c2_ick@a10ti,omap3-interface-clock|Nx i2c1_ick@a10ti,omap3-interface-clock|Nx uart2_ick@a10ti,omap3-interface-clock|Nx uart1_ick@a10ti,omap3-interface-clock|Nx  gpt11_ick@a10ti,omap3-interface-clock|Nx  gpt10_ick@a10ti,omap3-interface-clock|Nx  mcbsp5_ick@a10ti,omap3-interface-clock|Nx  mcbsp1_ick@a10ti,omap3-interface-clock|Nx  omapctrl_ick@a10ti,omap3-interface-clock|Nx dss_tv_fck@e00ti,gate-clock|<xdss_96m_fck@e00ti,gate-clock|Ixdss2_alwon_fck@e00ti,gate-clock|"xdummy_ck fixed-clock gpt1_gate_fck@c00ti,composite-gate-clock|"x Ogpt1_mux_fck@c40ti,composite-mux-clock|D"x @Pgpt1_fckti,composite-clock|OPaes2_ick@a10ti,omap3-interface-clock|Nx wkup_32k_fckfixed-factor-clock|DR]Qgpio1_dbck@c00ti,gate-clock|Qx sha12_ick@a10ti,omap3-interface-clock|Nx wdt2_fck@c00ti,wait-gate-clock|Qx wdt2_ick@c10ti,omap3-interface-clock|Rx wdt1_ick@c10ti,omap3-interface-clock|Rx gpio1_ick@c10ti,omap3-interface-clock|Rx omap_32ksync_ick@c10ti,omap3-interface-clock|Rx gpt12_ick@c10ti,omap3-interface-clock|Rx gpt1_ick@c10ti,omap3-interface-clock|Rx per_96m_fckfixed-factor-clock|-R] per_48m_fckfixed-factor-clock|4R]Suart3_fck@1000ti,wait-gate-clock|Sx gpt2_gate_fck@1000ti,composite-gate-clock|"xTgpt2_mux_fck@1040ti,composite-mux-clock|D"x@Ugpt2_fckti,composite-clock|TUgpt3_gate_fck@1000ti,composite-gate-clock|"xVgpt3_mux_fck@1040ti,composite-mux-clock|D"x@Wgpt3_fckti,composite-clock|VWgpt4_gate_fck@1000ti,composite-gate-clock|"xXgpt4_mux_fck@1040ti,composite-mux-clock|D"x@Ygpt4_fckti,composite-clock|XYgpt5_gate_fck@1000ti,composite-gate-clock|"xZgpt5_mux_fck@1040ti,composite-mux-clock|D"x@[gpt5_fckti,composite-clock|Z[gpt6_gate_fck@1000ti,composite-gate-clock|"x\gpt6_mux_fck@1040ti,composite-mux-clock|D"x@]gpt6_fckti,composite-clock|\]gpt7_gate_fck@1000ti,composite-gate-clock|"x^gpt7_mux_fck@1040ti,composite-mux-clock|D"x@_gpt7_fckti,composite-clock|^_gpt8_gate_fck@1000ti,composite-gate-clock|" x`gpt8_mux_fck@1040ti,composite-mux-clock|D"x@agpt8_fckti,composite-clock|`agpt9_gate_fck@1000ti,composite-gate-clock|" xbgpt9_mux_fck@1040ti,composite-mux-clock|D"x@cgpt9_fckti,composite-clock|bcper_32k_alwon_fckfixed-factor-clock|DR]dgpio6_dbck@1000ti,gate-clock|dxgpio5_dbck@1000ti,gate-clock|dxgpio4_dbck@1000ti,gate-clock|dxgpio3_dbck@1000ti,gate-clock|dxgpio2_dbck@1000ti,gate-clock|dx wdt3_fck@1000ti,wait-gate-clock|dx per_l4_ickfixed-factor-clock|CR]egpio6_ick@1010ti,omap3-interface-clock|exgpio5_ick@1010ti,omap3-interface-clock|exgpio4_ick@1010ti,omap3-interface-clock|exgpio3_ick@1010ti,omap3-interface-clock|exgpio2_ick@1010ti,omap3-interface-clock|ex wdt3_ick@1010ti,omap3-interface-clock|ex uart3_ick@1010ti,omap3-interface-clock|ex uart4_ick@1010ti,omap3-interface-clock|exgpt9_ick@1010ti,omap3-interface-clock|ex gpt8_ick@1010ti,omap3-interface-clock|ex gpt7_ick@1010ti,omap3-interface-clock|exgpt6_ick@1010ti,omap3-interface-clock|exgpt5_ick@1010ti,omap3-interface-clock|exgpt4_ick@1010ti,omap3-interface-clock|exgpt3_ick@1010ti,omap3-interface-clock|exgpt2_ick@1010ti,omap3-interface-clock|exmcbsp2_ick@1010ti,omap3-interface-clock|exmcbsp3_ick@1010ti,omap3-interface-clock|exmcbsp4_ick@1010ti,omap3-interface-clock|exmcbsp2_gate_fck@1000ti,composite-gate-clock|xmcbsp3_gate_fck@1000ti,composite-gate-clock|xmcbsp4_gate_fck@1000ti,composite-gate-clock|xemu_src_mux_ck@1140 ti,mux-clock|"fghx@iemu_src_ckti,clkdm-gate-clock|ijpclk_fck@1140ti,divider-clock|j0x@;pclkx2_fck@1140ti,divider-clock|j0x@;atclk_fck@1140ti,divider-clock|j0x@;traceclk_src_fck@1140 ti,mux-clock|"fghx@ktraceclk_fck@1140ti,divider-clock|k 0x@;secure_32k_fck fixed-clock lgpt12_fckfixed-factor-clock|lR]wdt1_fckfixed-factor-clock|lR]security_l4_ick2fixed-factor-clock|CR]maes1_ick@a14ti,omap3-interface-clock|mx rng_ick@a14ti,omap3-interface-clock|mx sha11_ick@a14ti,omap3-interface-clock|mx des1_ick@a14ti,omap3-interface-clock|mx cam_mclk@f00ti,gate-clock|nxcam_ick@f10!ti,omap3-no-wait-interface-clock|Cxcsi2_96m_fck@f00ti,gate-clock|xsecurity_l3_ickfixed-factor-clock|BR]opka_ick@a14ti,omap3-interface-clock|ox icr_ick@a10ti,omap3-interface-clock|Nx des2_ick@a10ti,omap3-interface-clock|Nx mspro_ick@a10ti,omap3-interface-clock|Nx mailboxes_ick@a10ti,omap3-interface-clock|Nx ssi_l4_ickfixed-factor-clock|CR]vsr1_fck@c00ti,wait-gate-clock|"x sr2_fck@c00ti,wait-gate-clock|"x sr_l4_ickfixed-factor-clock|CR]dpll2_fck@40ti,divider-clock|*0x@;pdpll2_ck@4ti,omap3-dpll-clock|"px$@4qdpll2_m2_ck@44ti,divider-clock|q0xD;riva2_ck@0ti,wait-gate-clock|rxmodem_fck@a00ti,omap3-interface-clock|"x sad2d_ick@a10ti,omap3-interface-clock|Bx mad2d_ick@a18ti,omap3-interface-clock|Bx mspro_fck@a00ti,wait-gate-clock|x ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock|#x sssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock|#x @$tssi_ssr_fck_3430es2ti,composite-clock|stussi_sst_fck_3430es2fixed-factor-clock|uR]hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock|Mx ssi_ick_3430es2@a10ti,omap3-ssi-interface-clock|vx usim_gate_fck@c00ti,composite-gate-clock|I x sys_d2_ckfixed-factor-clock|"R]xomap_96m_d2_fckfixed-factor-clock|IR]yomap_96m_d4_fckfixed-factor-clock|IR]zomap_96m_d8_fckfixed-factor-clock|IR]{omap_96m_d10_fckfixed-factor-clock|IR] |dpll5_m2_d4_ckfixed-factor-clock|wR]}dpll5_m2_d8_ckfixed-factor-clock|wR]~dpll5_m2_d16_ckfixed-factor-clock|wR]dpll5_m2_d20_ckfixed-factor-clock|wR]usim_mux_fck@c40ti,composite-mux-clock(|"xyz{|}~x @;usim_fckti,composite-clock|usim_ick@c10ti,omap3-interface-clock|Rx  dpll5_ck@d04ti,omap3-dpll-clock|""x  $ L 4dpll5_m2_ck@d50ti,divider-clock|0x P;wsgx_gate_fck@b00ti,composite-gate-clock|*x core_d3_ckfixed-factor-clock|*R]core_d4_ckfixed-factor-clock|*R]core_d6_ckfixed-factor-clock|*R]omap_192m_alwon_fckfixed-factor-clock|&R]core_d2_ckfixed-factor-clock|*R]sgx_mux_fck@b40ti,composite-mux-clock |.x @sgx_fckti,composite-clock| sgx_ick@b10ti,wait-gate-clock|Bx cpefuse_fck@a08ti,gate-clock|"x ts_fck@a08ti,gate-clock|Dx usbtll_fck@a08ti,wait-gate-clock|wx usbtll_ick@a18ti,omap3-interface-clock|Nx mmchs3_ick@a10ti,omap3-interface-clock|Nx mmchs3_fck@a00ti,wait-gate-clock|x dss1_alwon_fck_3430es2@e00ti,dss-gate-clock|xdss_ick_3430es2@e10ti,omap3-dss-interface-clock|Cxusbhost_120m_fck@1400ti,gate-clock|wxusbhost_48m_fck@1400ti,dss-gate-clock|4xusbhost_ick@1410ti,omap3-dss-interface-clock|Cxuart4_fck@1000ti,wait-gate-clock|Sxclockdomainscore_l3_clkdmti,clockdomain|dpll3_clkdmti,clockdomain|dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainl|emu_clkdmti,clockdomain|jdpll4_clkdmti,clockdomain| wkup_clkdmti,clockdomain$|dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|cam_clkdmti,clockdomain|iva2_clkdmti,clockdomain|dpll2_clkdmti,clockdomain|qd2d_clkdmti,clockdomain |dpll5_clkdmti,clockdomain|sgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |target-module@48320000ti,sysc-omap2ti,syscxH2H2 revsysc|Qfckick+ H2counter@0ti,omap-counter32kx interrupt-controller@48200000ti,omap3-intc xH target-module@48056000ti,sysc-omap2ti,syscxH`H`,H`(revsyscsyss#  |Mick+ H`dma-controller@0ti,omap3630-sdmati,omap-sdmax   !`gpio@48310000ti,omap3-gpioxH1gpio1.@P gpio@49050000ti,omap3-gpioxIgpio2@P gpio@49052000ti,omap3-gpioxI gpio3@P gpio@49054000ti,omap3-gpioxI@ gpio4@P gpio@49056000ti,omap3-gpioxI`!gpio5@P gpio@49058000ti,omap3-gpioxI"gpio6@P serial@4806a000ti,omap3-uartxH \H12txrxuart1 lpdefault~serial@4806c000ti,omap3-uartxH\I34txrxuart2 lpdefault~serial@49020000ti,omap3-uartxI\J56txrxuart3 lpdefault~i2c@48070000 ti,omap3-i2cxH8txrx+i2c1 '@twl@48xH  ti,twl4030 rtcti,twl4030-rtc bciti,twl4030-bci  vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpio@P twl4030-usbti,twl4030-usb pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madc+i2c@48072000 ti,omap3-i2cxH 9txrx+i2c2 i2c@48060000 ti,omap3-i2cxH=txrx+i2c3 tvp5146@5c ti,tvp5146m2x\mailbox@48094000ti,omap3-mailboxmailboxxH @=I[dsp m xspi@48098000ti,omap2-mcspixH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspixH B+mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspixH [+mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1=>txrxpdefault~mmc@480b4000ti,omap3-hsmmcxH @Vmmc2/0txrxmmc@480ad000ti,omap3-hsmmcxH ^mmc3MNtxrxpdefault~+wlcore@2 ti,wl1271x mmu@480bd400ti,omap2-iommuxH mmu_ispmmu@5d000000ti,omap2-iommux]mmu_iva  disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@mpu ;< 'commontxrx7mcbsp1 txrx|fck  disabledtarget-module@480a0000ti,sysc-omap2ti,syscxH <H @H Drevsyscsyss|ick+ H rng@0 ti,omap2-rngx 4mcbsp@49022000ti,omap3-mcbspxI I mpusidetone>?'commontxrxsidetone7mcbsp2mcbsp2_sidetone!"txrx|fckick  disabledmcbsp@49024000ti,omap3-mcbspxI@I mpusidetoneYZ'commontxrxsidetone7mcbsp3mcbsp3_sidetonetxrx|fckick  disabledmcbsp@49026000ti,omap3-mcbspxI`mpu 67 'commontxrx7mcbsp4txrx|fckF  disabledmcbsp@48096000ti,omap3-mcbspxH `mpu QR 'commontxrx7mcbsp5txrx|fck  disabledsham@480c3000ti,omap3-shamshamxH 0d1Erxtarget-module@48318000ti,sysc-omap2-timerti,syscxH1H1H1revsyscsyss' |fckick+ H1Wktimer@0ti,omap3430-timerx|fck%vDtarget-module@49032000ti,sysc-omap2-timerti,syscxI I I revsyscsyss' |fckick+ I timer@0ti,omap3430-timerx&timer@49034000ti,omap3430-timerxI@'timer3timer@49036000ti,omap3430-timerxI`(timer4timer@49038000ti,omap3430-timerxI)timer5timer@4903a000ti,omap3430-timerxI*timer6timer@4903c000ti,omap3430-timerxI+timer7timer@4903e000ti,omap3430-timerxI,timer8timer@49040000ti,omap3430-timerxI-timer9timer@48086000ti,omap3430-timerxH`.timer10timer@48088000ti,omap3430-timerxH/timer11target-module@48304000ti,sysc-omap2-timerti,syscxH0@H0@H0@revsyscsyss' |fckick+ H0@timer@0ti,omap3430-timerx_vusbhstll@48062000 ti,usbhs-tllxH N usb_tll_hsusbhshost@48064000ti,usbhs-hostxH@ usb_host_hs+ohci@48064400ti,ohci-omap3xHDLehci@48064800 ti,ehci-omapxHHMgpmc@6e000000ti,omap3430-gpmcgpmcxnrxtx+ @P ,ethernet@gpmcsmsc,lan9221smsc,lan9115 )C]k}(-- x/IK`Kz x uart@3,0 ns16550a x    ,>)C]k}((-- /I`z-uart@3,1 ns16550a x    uart@3,2 ns16550a x    uart@3,3 ns16550a x    usb_otg_hs@480ab000ti,omap3-musbxH \]'mcdma usb_otg_hsLW_ hw2dss@48050000 ti,omap3-dssxH  disabled dss_core|fck+dispc@48050400ti,omap3-dispcxH dss_dispc|fckencoder@4804fc00 ti,omap3-dsixHH@H protophypll  disabled dss_dsi1| fcksys_clk+encoder@48050800ti,omap3-rfbixH  disabled dss_rfbi|fckickencoder@48050c00ti,omap3-vencxH   disabled dss_venc|fcktv_dac_clkssi-controller@48058000 ti,omap3-ssissi okayxHHsysgddG'gdd_mpu+ |u ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portxHHtxrxCDssi-port@4805b000ti,omap3-ssi-portxHHtxrxEFserial@49042000ti,omap3-uartxI PQRtxrxuart4 l  disabledregulator-abb-mpu ti,abb-v1 abb_mpu_iva+xH0rH0hbase-addressint-address|"`sO7pinmux@480025a0 ti,omap3-padconfpinctrl-singlexH%\+ 0Npinmux_mmc3_2_pins(k8DFHBisp@480bc000 ti,omap3-ispxH H ports+bandgap@48002524xH%$ti,omap36xx-bandgap target-module@480cb000ti,sysc-omap3630-srti,syscsmartreflex_corexH 8sysc |fck+ H smartreflex@0ti,omap3-smartreflex-corextarget-module@480c9000ti,sysc-omap3630-srti,syscsmartreflex_mpu_ivaxH 8sysc |fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivaxtarget-module@50000000ti,sysc-omap4ti,syscxPP revsysc  | fckick+ Popp-tableoperating-points-v2-ti-cpuopp50-300000000ssssss  opp100-600000000#FOOOOOO opp130-800000000/777777 opp1g-1000000000;  &opp_supplyti,omap-opp-supply 1thermal-zonescpu_thermal L b pN  } tripscpu_alert 8 spassive cpu_crit _  scriticalcooling-mapsmap0    regulator-vddvarioregulator-fixed vddvario regulator-vdd33aregulator-fixedvdd33a memory@80000000lmemoryx wl12xx_vmmcpdefault~ regulator-fixedvwl1271w@w@  p  compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supply#cooling-cellscpu0-supplyphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyio-channelsio-channel-namesti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvqmmc-supplybus-widthnon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,#tlb-entriesstatusinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressreg-shiftcurrent-speedgpmc,mux-add-datagpmc,wait-pinmultipointnum-epsram-bitsinterface-typeusb-phypowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modeti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-deviceregulator-always-ongpiostartup-delay-usenable-active-high