.8( z|Stechnexion,omap3-thundertechnexion,omap3-tao3530ti,omap3430ti,omap34xxti,omap3 +,7TI OMAP3 Thunder baseboard with TAO3530 SOMchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpu pmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+&Dpinmux_hsusbb2_pins`a          pinmux_mmc1_pinsPa "$&pinmux_mmc2_pins0a(*,.02pinmux_wlan_gpioa^pinmux_uart3_pinsanAppinmux_i2c3_pinsapinmux_mcspi1_pins apinmux_mcspi3_pins apinmux_mcbsp3_pins a<>@Bpinmux_twl4030_pinsaApinmux_dss_dpi_pinsapinmux_lte430_pinsa8pinmux_backlight_pinsa:scm_conf@270sysconsimple-busyp0+ p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapyupbias_mmc_omap2430|pbias_mmc_omap2430w@-clocks+mcbsp5_mux_fck@68ti,composite-mux-clock}yh mcbsp5_fckti,composite-clock} mcbsp1_mux_fck@4ti,composite-mux-clock}y mcbsp1_fckti,composite-clock} mcbsp2_mux_fck@4ti,composite-mux-clock} ymcbsp2_fckti,composite-clock} mcbsp3_mux_fck@68ti,composite-mux-clock} yhmcbsp3_fckti,composite-clock}mcbsp4_mux_fck@68ti,composite-mux-clock} yhmcbsp4_fckti,composite-clock}clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+&Dpinmux_twl4030_vpins atarget-module@480a6000ti,sysc-omap2ti,syscyH `DH `HH `Lrevsyscsyss }ick+ H `  disabledaes1@0 ti,omap3-aesyP  txrxtarget-module@480c5000ti,sysc-omap2ti,syscyH PDH PHH PLrevsyscsyss }ick+ H P  disabledaes2@0 ti,omap3-aesyPABtxrxprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockYosc_sys_ck@d40 ti,mux-clock}y @sys_ck@1270ti,divider-clock}-yp8!sys_clkout1@d70ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock}OZdpll3_m2x2_ckfixed-factor-clock}OZ dpll4_x2_ckfixed-factor-clock}OZcorex2_fckfixed-factor-clock} OZ"wkup_l4_ickfixed-factor-clock}!OZQcorex2_d3_fckfixed-factor-clock}"OZcorex2_d5_fckfixed-factor-clock}"OZclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockCvirt_12m_ck fixed-clockvirt_13m_ck fixed-clock]@virt_19200000_ck fixed-clock$virt_26000000_ck fixed-clockvirt_38_4m_ck fixed-clockIdpll4_ck@d00ti,omap3-dpll-per-clock}!!y D 0dpll4_m2_ck@d48ti,divider-clock}-?y H8#dpll4_m2x2_mul_ckfixed-factor-clock}#OZ$dpll4_m2x2_ck@d00ti,gate-clock}$y d%omap_96m_alwon_fckfixed-factor-clock}%OZ,dpll3_ck@d00ti,omap3-dpll-core-clock}!!y @ 0dpll3_m3_ck@1140ti,divider-clock}-y@8&dpll3_m3x2_mul_ckfixed-factor-clock}&OZ'dpll3_m3x2_ck@d00ti,gate-clock}' y d(emu_core_alwon_ckfixed-factor-clock}(OZesys_altclk fixed-clock1mcbsp_clks fixed-clockdpll3_m2_ck@d40ti,divider-clock}-y @8core_ckfixed-factor-clock}OZ)dpll1_fck@940ti,divider-clock})-y @8*dpll1_ck@904ti,omap3-dpll-clock}!*y  $ @ 4dpll1_x2_ckfixed-factor-clock}OZ+dpll1_x2m2_ck@944ti,divider-clock}+-y D8?cm_96m_fckfixed-factor-clock},OZ-omap_96m_fck@d40 ti,mux-clock}-!y @Hdpll4_m3_ck@e40ti,divider-clock}- y@8.dpll4_m3x2_mul_ckfixed-factor-clock}.OZ/dpll4_m3x2_ck@d00ti,gate-clock}/y d0omap_54m_fck@d40 ti,mux-clock}01y @;cm_96m_d2_fckfixed-factor-clock}-OZ2omap_48m_fck@d40 ti,mux-clock}21y @3omap_12m_fckfixed-factor-clock}3OZJdpll4_m4_ck@e40ti,divider-clock}-y@84dpll4_m4x2_mul_ckti,fixed-factor-clock}4z5dpll4_m4x2_ck@d00ti,gate-clock}5y ddpll4_m5_ck@f40ti,divider-clock}-?y@86dpll4_m5x2_mul_ckti,fixed-factor-clock}6z7dpll4_m5x2_ck@d00ti,gate-clock}7y dmdpll4_m6_ck@1140ti,divider-clock}-?y@88dpll4_m6x2_mul_ckfixed-factor-clock}8OZ9dpll4_m6x2_ck@d00ti,gate-clock}9y d:emu_per_alwon_ckfixed-factor-clock}:OZfclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock})y p<clkout2_src_mux_ck@d70ti,composite-mux-clock})!-;y p=clkout2_src_ckti,composite-clock}<=>sys_clkout2@d70ti,divider-clock}>-@y pmpu_ckfixed-factor-clock}?OZ@arm_fck@924ti,divider-clock}@y $-emu_mpu_alwon_ckfixed-factor-clock}@OZgl3_ick@a40ti,divider-clock})-y @8Al4_ick@a40ti,divider-clock}A-y @8Brm_ick@c40ti,divider-clock}B-y @8gpt10_gate_fck@a00ti,composite-gate-clock}! y Dgpt10_mux_fck@a40ti,composite-mux-clock}C!y @Egpt10_fckti,composite-clock}DEgpt11_gate_fck@a00ti,composite-gate-clock}! y Fgpt11_mux_fck@a40ti,composite-mux-clock}C!y @Ggpt11_fckti,composite-clock}FGcore_96m_fckfixed-factor-clock}HOZmmchs2_fck@a00ti,wait-gate-clock}y mmchs1_fck@a00ti,wait-gate-clock}y i2c3_fck@a00ti,wait-gate-clock}y i2c2_fck@a00ti,wait-gate-clock}y i2c1_fck@a00ti,wait-gate-clock}y mcbsp5_gate_fck@a00ti,composite-gate-clock} y mcbsp1_gate_fck@a00ti,composite-gate-clock} y  core_48m_fckfixed-factor-clock}3OZImcspi4_fck@a00ti,wait-gate-clock}Iy mcspi3_fck@a00ti,wait-gate-clock}Iy mcspi2_fck@a00ti,wait-gate-clock}Iy mcspi1_fck@a00ti,wait-gate-clock}Iy uart2_fck@a00ti,wait-gate-clock}Iy uart1_fck@a00ti,wait-gate-clock}Iy  core_12m_fckfixed-factor-clock}JOZKhdq_fck@a00ti,wait-gate-clock}Ky core_l3_ickfixed-factor-clock}AOZLsdrc_ick@a10ti,wait-gate-clock}Ly gpmc_fckfixed-factor-clock}LOZcore_l4_ickfixed-factor-clock}BOZMmmchs2_ick@a10ti,omap3-interface-clock}My mmchs1_ick@a10ti,omap3-interface-clock}My hdq_ick@a10ti,omap3-interface-clock}My mcspi4_ick@a10ti,omap3-interface-clock}My mcspi3_ick@a10ti,omap3-interface-clock}My mcspi2_ick@a10ti,omap3-interface-clock}My mcspi1_ick@a10ti,omap3-interface-clock}My i2c3_ick@a10ti,omap3-interface-clock}My i2c2_ick@a10ti,omap3-interface-clock}My i2c1_ick@a10ti,omap3-interface-clock}My uart2_ick@a10ti,omap3-interface-clock}My uart1_ick@a10ti,omap3-interface-clock}My  gpt11_ick@a10ti,omap3-interface-clock}My  gpt10_ick@a10ti,omap3-interface-clock}My  mcbsp5_ick@a10ti,omap3-interface-clock}My  mcbsp1_ick@a10ti,omap3-interface-clock}My  omapctrl_ick@a10ti,omap3-interface-clock}My dss_tv_fck@e00ti,gate-clock};ydss_96m_fck@e00ti,gate-clock}Hydss2_alwon_fck@e00ti,gate-clock}!ydummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock}!y Ngpt1_mux_fck@c40ti,composite-mux-clock}C!y @Ogpt1_fckti,composite-clock}NOaes2_ick@a10ti,omap3-interface-clock}My wkup_32k_fckfixed-factor-clock}COZPgpio1_dbck@c00ti,gate-clock}Py sha12_ick@a10ti,omap3-interface-clock}My wdt2_fck@c00ti,wait-gate-clock}Py wdt2_ick@c10ti,omap3-interface-clock}Qy wdt1_ick@c10ti,omap3-interface-clock}Qy gpio1_ick@c10ti,omap3-interface-clock}Qy omap_32ksync_ick@c10ti,omap3-interface-clock}Qy gpt12_ick@c10ti,omap3-interface-clock}Qy gpt1_ick@c10ti,omap3-interface-clock}Qy per_96m_fckfixed-factor-clock},OZ per_48m_fckfixed-factor-clock}3OZRuart3_fck@1000ti,wait-gate-clock}Ry gpt2_gate_fck@1000ti,composite-gate-clock}!ySgpt2_mux_fck@1040ti,composite-mux-clock}C!y@Tgpt2_fckti,composite-clock}STgpt3_gate_fck@1000ti,composite-gate-clock}!yUgpt3_mux_fck@1040ti,composite-mux-clock}C!y@Vgpt3_fckti,composite-clock}UVgpt4_gate_fck@1000ti,composite-gate-clock}!yWgpt4_mux_fck@1040ti,composite-mux-clock}C!y@Xgpt4_fckti,composite-clock}WXgpt5_gate_fck@1000ti,composite-gate-clock}!yYgpt5_mux_fck@1040ti,composite-mux-clock}C!y@Zgpt5_fckti,composite-clock}YZgpt6_gate_fck@1000ti,composite-gate-clock}!y[gpt6_mux_fck@1040ti,composite-mux-clock}C!y@\gpt6_fckti,composite-clock}[\gpt7_gate_fck@1000ti,composite-gate-clock}!y]gpt7_mux_fck@1040ti,composite-mux-clock}C!y@^gpt7_fckti,composite-clock}]^gpt8_gate_fck@1000ti,composite-gate-clock}! y_gpt8_mux_fck@1040ti,composite-mux-clock}C!y@`gpt8_fckti,composite-clock}_`gpt9_gate_fck@1000ti,composite-gate-clock}! yagpt9_mux_fck@1040ti,composite-mux-clock}C!y@bgpt9_fckti,composite-clock}abper_32k_alwon_fckfixed-factor-clock}COZcgpio6_dbck@1000ti,gate-clock}cygpio5_dbck@1000ti,gate-clock}cygpio4_dbck@1000ti,gate-clock}cygpio3_dbck@1000ti,gate-clock}cygpio2_dbck@1000ti,gate-clock}cy wdt3_fck@1000ti,wait-gate-clock}cy per_l4_ickfixed-factor-clock}BOZdgpio6_ick@1010ti,omap3-interface-clock}dygpio5_ick@1010ti,omap3-interface-clock}dygpio4_ick@1010ti,omap3-interface-clock}dygpio3_ick@1010ti,omap3-interface-clock}dygpio2_ick@1010ti,omap3-interface-clock}dy wdt3_ick@1010ti,omap3-interface-clock}dy uart3_ick@1010ti,omap3-interface-clock}dy uart4_ick@1010ti,omap3-interface-clock}dygpt9_ick@1010ti,omap3-interface-clock}dy gpt8_ick@1010ti,omap3-interface-clock}dy gpt7_ick@1010ti,omap3-interface-clock}dygpt6_ick@1010ti,omap3-interface-clock}dygpt5_ick@1010ti,omap3-interface-clock}dygpt4_ick@1010ti,omap3-interface-clock}dygpt3_ick@1010ti,omap3-interface-clock}dygpt2_ick@1010ti,omap3-interface-clock}dymcbsp2_ick@1010ti,omap3-interface-clock}dymcbsp3_ick@1010ti,omap3-interface-clock}dymcbsp4_ick@1010ti,omap3-interface-clock}dymcbsp2_gate_fck@1000ti,composite-gate-clock}y mcbsp3_gate_fck@1000ti,composite-gate-clock}ymcbsp4_gate_fck@1000ti,composite-gate-clock}yemu_src_mux_ck@1140 ti,mux-clock}!efgy@hemu_src_ckti,clkdm-gate-clock}hipclk_fck@1140ti,divider-clock}i-y@8pclkx2_fck@1140ti,divider-clock}i-y@8atclk_fck@1140ti,divider-clock}i-y@8traceclk_src_fck@1140 ti,mux-clock}!efgy@jtraceclk_fck@1140ti,divider-clock}j -y@8secure_32k_fck fixed-clockkgpt12_fckfixed-factor-clock}kOZwdt1_fckfixed-factor-clock}kOZsecurity_l4_ick2fixed-factor-clock}BOZlaes1_ick@a14ti,omap3-interface-clock}ly rng_ick@a14ti,omap3-interface-clock}ly sha11_ick@a14ti,omap3-interface-clock}ly des1_ick@a14ti,omap3-interface-clock}ly cam_mclk@f00ti,gate-clock}mycam_ick@f10!ti,omap3-no-wait-interface-clock}Bycsi2_96m_fck@f00ti,gate-clock}ysecurity_l3_ickfixed-factor-clock}AOZnpka_ick@a14ti,omap3-interface-clock}ny icr_ick@a10ti,omap3-interface-clock}My des2_ick@a10ti,omap3-interface-clock}My mspro_ick@a10ti,omap3-interface-clock}My mailboxes_ick@a10ti,omap3-interface-clock}My ssi_l4_ickfixed-factor-clock}BOZusr1_fck@c00ti,wait-gate-clock}!y  sr2_fck@c00ti,wait-gate-clock}!y sr_l4_ickfixed-factor-clock}BOZdpll2_fck@40ti,divider-clock})-y@8odpll2_ck@4ti,omap3-dpll-clock}!oy$@4pdpll2_m2_ck@44ti,divider-clock}p-yD8qiva2_ck@0ti,wait-gate-clock}qymodem_fck@a00ti,omap3-interface-clock}!y sad2d_ick@a10ti,omap3-interface-clock}Ay mad2d_ick@a18ti,omap3-interface-clock}Ay mspro_fck@a00ti,wait-gate-clock}y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock}"y rssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock}"y @$sssi_ssr_fck_3430es2ti,composite-clock}rstssi_sst_fck_3430es2fixed-factor-clock}tOZhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Ly ssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}uy usim_gate_fck@c00ti,composite-gate-clock}H y sys_d2_ckfixed-factor-clock}!OZwomap_96m_d2_fckfixed-factor-clock}HOZxomap_96m_d4_fckfixed-factor-clock}HOZyomap_96m_d8_fckfixed-factor-clock}HOZzomap_96m_d10_fckfixed-factor-clock}HOZ {dpll5_m2_d4_ckfixed-factor-clock}vOZ|dpll5_m2_d8_ckfixed-factor-clock}vOZ}dpll5_m2_d16_ckfixed-factor-clock}vOZ~dpll5_m2_d20_ckfixed-factor-clock}vOZusim_mux_fck@c40ti,composite-mux-clock(}!wxyz{|}~y @8usim_fckti,composite-clock}usim_ick@c10ti,omap3-interface-clock}Qy  dpll5_ck@d04ti,omap3-dpll-clock}!!y  $ L 4dpll5_m2_ck@d50ti,divider-clock}-y P8vsgx_gate_fck@b00ti,composite-gate-clock})y core_d3_ckfixed-factor-clock})OZcore_d4_ckfixed-factor-clock})OZcore_d6_ckfixed-factor-clock})OZomap_192m_alwon_fckfixed-factor-clock}%OZcore_d2_ckfixed-factor-clock})OZsgx_mux_fck@b40ti,composite-mux-clock }-y @sgx_fckti,composite-clock} sgx_ick@b10ti,wait-gate-clock}Ay cpefuse_fck@a08ti,gate-clock}!y ts_fck@a08ti,gate-clock}Cy usbtll_fck@a08ti,wait-gate-clock}vy usbtll_ick@a18ti,omap3-interface-clock}My mmchs3_ick@a10ti,omap3-interface-clock}My mmchs3_fck@a00ti,wait-gate-clock}y dss1_alwon_fck_3430es2@e00ti,dss-gate-clock}ydss_ick_3430es2@e10ti,omap3-dss-interface-clock}Byusbhost_120m_fck@1400ti,gate-clock}vyusbhost_48m_fck@1400ti,dss-gate-clock}3yusbhost_ick@1410ti,omap3-dss-interface-clock}Byclockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}idpll4_clkdmti,clockdomain}wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}pd2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }target-module@48320000ti,sysc-omap2ti,syscyH2H2 revsysc}Pfckick+ H2counter@0ti,omap-counter32ky interrupt-controller@48200000ti,omap3-intcyH target-module@48056000ti,sysc-omap2ti,syscyH`H`,H`(revsyscsyss#  }Lick+ H`dma-controller@0ti,omap3430-sdmati,omap-sdmay  `gpio@48310000ti,omap3-gpioyH1gpio1+=Mgpio@49050000ti,omap3-gpioyIgpio2=Mgpio@49052000ti,omap3-gpioyI gpio3=Mgpio@49054000ti,omap3-gpioyI@ gpio4=Mgpio@49056000ti,omap3-gpioyI`!gpio5=Mgpio@49058000ti,omap3-gpioyI"gpio6=Mserial@4806a000ti,omap3-uartyH YH12txrxuart1lserial@4806c000ti,omap3-uartyHYI34txrxuart2lserial@49020000ti,omap3-uartyIYJ56txrxuart3lmdefault{i2c@48070000 ti,omap3-i2cyH8txrx+i2c1'@twl@48yH  ti,twl4030mdefault{audioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci  vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2 |vdd_ehciw@w@regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpio=Mtwl4030-usbti,twl4030-usb pwmti,twl4030-pwm&pwmledti,twl4030-pwmled&pwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad1Amadcti,twl4030-madcTi2c@48072000 ti,omap3-i2cyH 9txrx+i2c2i2c@48060000 ti,omap3-i2cyH=txrx+i2c3mdefault{mailbox@48094000ti,omap3-mailboxmailboxyH @frdsp  spi@48098000ti,omap2-mcspiyH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3mdefault{spidev@0spidevlyspi@4809a000ti,omap2-mcspiyH B+mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [+mcspi3 tx0rx0tx1rx1mdefault{spidev@0spidevlyspi@480ba000ti,omap2-mcspiyH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-hsmmcyH Smmc1=>txrxmdefault{ mmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrxmdefault{)mmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400<ti,omap2-iommuyH mmu_ispImmu@5d000000<ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< Ycommontxrximcbsp1 txrx}fck disabledtarget-module@480a0000ti,sysc-omap2ti,syscyH <H @H Drevsyscsyss}ick+ H rng@0 ti,omap2-rngy 4mcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?Ycommontxrxsidetoneimcbsp2mcbsp2_sidetone!"txrx}fckickokaymcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZYcommontxrxsidetoneimcbsp3mcbsp3_sidetonetxrx}fckickokaymdefault{mcbsp@49026000ti,omap3-mcbspyI`mpu 67 Ycommontxrximcbsp4txrx}fckx disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR Ycommontxrximcbsp5txrx}fck disabledsham@480c3000ti,omap3-shamshamyH 0d1Erx disabledtarget-module@48318000ti,sysc-omap2-timerti,syscyH1H1H1revsyscsyss' }fckick+ H1timer@0ti,omap3430-timery}fck%Ctarget-module@49032000ti,sysc-omap2-timerti,syscyI I I revsyscsyss' }fckick+ I timer@0ti,omap3430-timery&timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5timer@4903a000ti,omap3430-timeryI*timer6timer@4903c000ti,omap3430-timeryI+timer7timer@4903e000ti,omap3430-timeryI,timer8timer@49040000ti,omap3430-timeryI-timer9timer@48086000ti,omap3430-timeryH`.timer10timer@48088000ti,omap3430-timeryH/timer11target-module@48304000ti,sysc-omap2-timerti,syscyH0@H0@H0@revsyscsyss' }fckick+ H0@timer@0ti,omap3430-timery_usbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs+ ehci-phyohci@48064400ti,ohci-omap3yHDLehci@48064800 ti,ehci-omapyHHM+gpmc@6e000000ti,omap3430-gpmcgpmcynrxtx0<+=M0nand@0,0ti,omap2-nand y N]osw$$$0 H1HB6Q+x-loader@0 cX-Loaderybootloaders@80000cU-Bootybootloaders_env@260000 cU-Boot Envy&kernel@280000cKernely(@filesystem@680000 cFile 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P@opp-tableoperating-points-v2-ti-cpuuopp1-125000000sY@ opp2-250000000沀 g8g8g8opp3-500000000e OOOopp4-550000000 U txtxtxopp5-600000000#F pppopp6-720000000*T ppp"thermal-zonescpu_thermal-CQN ^ tripscpu_alertn8ztpassive cpu_critn_z tcriticalcooling-mapsmap0   memory@80000000mmemoryyhsusb2_power_regregulator-fixed |hsusb2_vbus2Z2Z phsusb2_phyusb-nop-xceiv soundti,omap-twl4030 omap3beagleregulator-mmc2-sdio-poweronregulator-fixed|regulator-mmc2-sdio-poweron00 'displaysamsung,lte430wq-f0cpanel-dpiclcdmdefault{  portendpointpanel-timingT@  *  $ 1  ; H U _backlightgpio-backlightmdefault{    o compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-points-v2#cooling-cellscpu0-supplyphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskstatusdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyspi-cphati,dual-voltpbias-supplyvmmc-supplyvqmmc-supplycd-gpiosbus-widthnon-removablecap-power-off-card#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,wr-access-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicegpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-on