#8( "ti,omap3-evmti,omap3430ti,omap3 +7TI OMAP35XX EVM (TMDSEVM3530)chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpupmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+&Dadefaultopinmux_twl4030_pinsyApinmux_dss_dpi_pins2ypinmux_mmc1_pinsPy "$&pinmux_mmc2_pinsPy(*,.02468:pinmux_uart3_pinsynAppinmux_ehci_port_select_pinsypinmux_hsusb2_pins0y      pinmux_wl12xx_gpioyPNpinmux_smsc911x_pinsyscm_conf@270sysconsimple-busyp0+ p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapypbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+mcbsp5_mux_fck@68ti,composite-mux-clock} yh mcbsp5_fckti,composite-clock} mcbsp1_mux_fck@4ti,composite-mux-clock} y mcbsp1_fckti,composite-clock} mcbsp2_mux_fck@4ti,composite-mux-clock} ymcbsp2_fckti,composite-clock}mcbsp3_mux_fck@68ti,composite-mux-clock} yhmcbsp3_fckti,composite-clock}mcbsp4_mux_fck@68ti,composite-mux-clock} yhmcbsp4_fckti,composite-clock}clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+&Dpinmux_twl4030_vpins ypinmux_dss_dpi_pins10y   target-module@480a6000ti,sysc-omap2ti,syscyH `DH `HH `Lrevsyscsyss }ick+ H ` aes1@0 ti,omap3-aesyP  $txrxtarget-module@480c5000ti,sysc-omap2ti,syscyH PDH PHH PLrevsyscsyss }ick+ H P aes2@0 ti,omap3-aesyPAB$txrxprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clock.Yosc_sys_ck@d40 ti,mux-clock}y @sys_ck@1270ti,divider-clock}>ypI#sys_clkout1@d70ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock}`kdpll3_m2x2_ckfixed-factor-clock} `k"dpll4_x2_ckfixed-factor-clock}!`kcorex2_fckfixed-factor-clock}"`k$wkup_l4_ickfixed-factor-clock}#`kScorex2_d3_fckfixed-factor-clock}$`kcorex2_d5_fckfixed-factor-clock}$`kclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clock.omap_32k_fck fixed-clock.Evirt_12m_ck fixed-clock.virt_13m_ck fixed-clock.]@virt_19200000_ck fixed-clock.$virt_26000000_ck fixed-clock.virt_38_4m_ck fixed-clock.Idpll4_ck@d00ti,omap3-dpll-per-clock}##y D 0!dpll4_m2_ck@d48ti,divider-clock}!>?y HI%dpll4_m2x2_mul_ckfixed-factor-clock}%`k&dpll4_m2x2_ck@d00ti,gate-clock}&y u'omap_96m_alwon_fckfixed-factor-clock}'`k.dpll3_ck@d00ti,omap3-dpll-core-clock}##y @ 0dpll3_m3_ck@1140ti,divider-clock}>y@I(dpll3_m3x2_mul_ckfixed-factor-clock}(`k)dpll3_m3x2_ck@d00ti,gate-clock}) y u*emu_core_alwon_ckfixed-factor-clock}*`kgsys_altclk fixed-clock.3mcbsp_clks fixed-clock. dpll3_m2_ck@d40ti,divider-clock}>y @I core_ckfixed-factor-clock} `k+dpll1_fck@940ti,divider-clock}+>y @I,dpll1_ck@904ti,omap3-dpll-clock}#,y  $ @ 4dpll1_x2_ckfixed-factor-clock}`k-dpll1_x2m2_ck@944ti,divider-clock}->y DIAcm_96m_fckfixed-factor-clock}.`k/omap_96m_fck@d40 ti,mux-clock}/#y @Jdpll4_m3_ck@e40ti,divider-clock}!> y@I0dpll4_m3x2_mul_ckfixed-factor-clock}0`k1dpll4_m3x2_ck@d00ti,gate-clock}1y u2omap_54m_fck@d40 ti,mux-clock}23y @=cm_96m_d2_fckfixed-factor-clock}/`k4omap_48m_fck@d40 ti,mux-clock}43y @5omap_12m_fckfixed-factor-clock}5`kLdpll4_m4_ck@e40ti,divider-clock}!>y@I6dpll4_m4x2_mul_ckti,fixed-factor-clock}67dpll4_m4x2_ck@d00ti,gate-clock}7y udpll4_m5_ck@f40ti,divider-clock}!>?y@I8dpll4_m5x2_mul_ckti,fixed-factor-clock}89dpll4_m5x2_ck@d00ti,gate-clock}9y uodpll4_m6_ck@1140ti,divider-clock}!>?y@I:dpll4_m6x2_mul_ckfixed-factor-clock}:`k;dpll4_m6x2_ck@d00ti,gate-clock};y u<emu_per_alwon_ckfixed-factor-clock}<`khclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}+y p>clkout2_src_mux_ck@d70ti,composite-mux-clock}+#/=y p?clkout2_src_ckti,composite-clock}>?@sys_clkout2@d70ti,divider-clock}@>@y pmpu_ckfixed-factor-clock}A`kBarm_fck@924ti,divider-clock}By $>emu_mpu_alwon_ckfixed-factor-clock}B`kil3_ick@a40ti,divider-clock}+>y @ICl4_ick@a40ti,divider-clock}C>y @IDrm_ick@c40ti,divider-clock}D>y @Igpt10_gate_fck@a00ti,composite-gate-clock}# y Fgpt10_mux_fck@a40ti,composite-mux-clock}E#y @Ggpt10_fckti,composite-clock}FGgpt11_gate_fck@a00ti,composite-gate-clock}# y Hgpt11_mux_fck@a40ti,composite-mux-clock}E#y @Igpt11_fckti,composite-clock}HIcore_96m_fckfixed-factor-clock}J`kmmchs2_fck@a00ti,wait-gate-clock}y mmchs1_fck@a00ti,wait-gate-clock}y i2c3_fck@a00ti,wait-gate-clock}y i2c2_fck@a00ti,wait-gate-clock}y i2c1_fck@a00ti,wait-gate-clock}y mcbsp5_gate_fck@a00ti,composite-gate-clock}  y  mcbsp1_gate_fck@a00ti,composite-gate-clock}  y  core_48m_fckfixed-factor-clock}5`kKmcspi4_fck@a00ti,wait-gate-clock}Ky mcspi3_fck@a00ti,wait-gate-clock}Ky mcspi2_fck@a00ti,wait-gate-clock}Ky mcspi1_fck@a00ti,wait-gate-clock}Ky uart2_fck@a00ti,wait-gate-clock}Ky uart1_fck@a00ti,wait-gate-clock}Ky  core_12m_fckfixed-factor-clock}L`kMhdq_fck@a00ti,wait-gate-clock}My core_l3_ickfixed-factor-clock}C`kNsdrc_ick@a10ti,wait-gate-clock}Ny gpmc_fckfixed-factor-clock}N`kcore_l4_ickfixed-factor-clock}D`kOmmchs2_ick@a10ti,omap3-interface-clock}Oy mmchs1_ick@a10ti,omap3-interface-clock}Oy hdq_ick@a10ti,omap3-interface-clock}Oy mcspi4_ick@a10ti,omap3-interface-clock}Oy mcspi3_ick@a10ti,omap3-interface-clock}Oy mcspi2_ick@a10ti,omap3-interface-clock}Oy mcspi1_ick@a10ti,omap3-interface-clock}Oy i2c3_ick@a10ti,omap3-interface-clock}Oy i2c2_ick@a10ti,omap3-interface-clock}Oy i2c1_ick@a10ti,omap3-interface-clock}Oy uart2_ick@a10ti,omap3-interface-clock}Oy uart1_ick@a10ti,omap3-interface-clock}Oy  gpt11_ick@a10ti,omap3-interface-clock}Oy  gpt10_ick@a10ti,omap3-interface-clock}Oy  mcbsp5_ick@a10ti,omap3-interface-clock}Oy  mcbsp1_ick@a10ti,omap3-interface-clock}Oy  omapctrl_ick@a10ti,omap3-interface-clock}Oy dss_tv_fck@e00ti,gate-clock}=ydss_96m_fck@e00ti,gate-clock}Jydss2_alwon_fck@e00ti,gate-clock}#ydummy_ck fixed-clock.gpt1_gate_fck@c00ti,composite-gate-clock}#y Pgpt1_mux_fck@c40ti,composite-mux-clock}E#y @Qgpt1_fckti,composite-clock}PQaes2_ick@a10ti,omap3-interface-clock}Oy wkup_32k_fckfixed-factor-clock}E`kRgpio1_dbck@c00ti,gate-clock}Ry sha12_ick@a10ti,omap3-interface-clock}Oy wdt2_fck@c00ti,wait-gate-clock}Ry wdt2_ick@c10ti,omap3-interface-clock}Sy wdt1_ick@c10ti,omap3-interface-clock}Sy gpio1_ick@c10ti,omap3-interface-clock}Sy omap_32ksync_ick@c10ti,omap3-interface-clock}Sy gpt12_ick@c10ti,omap3-interface-clock}Sy gpt1_ick@c10ti,omap3-interface-clock}Sy per_96m_fckfixed-factor-clock}.`kper_48m_fckfixed-factor-clock}5`kTuart3_fck@1000ti,wait-gate-clock}Ty gpt2_gate_fck@1000ti,composite-gate-clock}#yUgpt2_mux_fck@1040ti,composite-mux-clock}E#y@Vgpt2_fckti,composite-clock}UVgpt3_gate_fck@1000ti,composite-gate-clock}#yWgpt3_mux_fck@1040ti,composite-mux-clock}E#y@Xgpt3_fckti,composite-clock}WXgpt4_gate_fck@1000ti,composite-gate-clock}#yYgpt4_mux_fck@1040ti,composite-mux-clock}E#y@Zgpt4_fckti,composite-clock}YZgpt5_gate_fck@1000ti,composite-gate-clock}#y[gpt5_mux_fck@1040ti,composite-mux-clock}E#y@\gpt5_fckti,composite-clock}[\gpt6_gate_fck@1000ti,composite-gate-clock}#y]gpt6_mux_fck@1040ti,composite-mux-clock}E#y@^gpt6_fckti,composite-clock}]^gpt7_gate_fck@1000ti,composite-gate-clock}#y_gpt7_mux_fck@1040ti,composite-mux-clock}E#y@`gpt7_fckti,composite-clock}_`gpt8_gate_fck@1000ti,composite-gate-clock}# yagpt8_mux_fck@1040ti,composite-mux-clock}E#y@bgpt8_fckti,composite-clock}abgpt9_gate_fck@1000ti,composite-gate-clock}# ycgpt9_mux_fck@1040ti,composite-mux-clock}E#y@dgpt9_fckti,composite-clock}cdper_32k_alwon_fckfixed-factor-clock}E`kegpio6_dbck@1000ti,gate-clock}eygpio5_dbck@1000ti,gate-clock}eygpio4_dbck@1000ti,gate-clock}eygpio3_dbck@1000ti,gate-clock}eygpio2_dbck@1000ti,gate-clock}ey wdt3_fck@1000ti,wait-gate-clock}ey per_l4_ickfixed-factor-clock}D`kfgpio6_ick@1010ti,omap3-interface-clock}fygpio5_ick@1010ti,omap3-interface-clock}fygpio4_ick@1010ti,omap3-interface-clock}fygpio3_ick@1010ti,omap3-interface-clock}fygpio2_ick@1010ti,omap3-interface-clock}fy wdt3_ick@1010ti,omap3-interface-clock}fy uart3_ick@1010ti,omap3-interface-clock}fy uart4_ick@1010ti,omap3-interface-clock}fygpt9_ick@1010ti,omap3-interface-clock}fy gpt8_ick@1010ti,omap3-interface-clock}fy gpt7_ick@1010ti,omap3-interface-clock}fygpt6_ick@1010ti,omap3-interface-clock}fygpt5_ick@1010ti,omap3-interface-clock}fygpt4_ick@1010ti,omap3-interface-clock}fygpt3_ick@1010ti,omap3-interface-clock}fygpt2_ick@1010ti,omap3-interface-clock}fymcbsp2_ick@1010ti,omap3-interface-clock}fymcbsp3_ick@1010ti,omap3-interface-clock}fymcbsp4_ick@1010ti,omap3-interface-clock}fymcbsp2_gate_fck@1000ti,composite-gate-clock} ymcbsp3_gate_fck@1000ti,composite-gate-clock} ymcbsp4_gate_fck@1000ti,composite-gate-clock} yemu_src_mux_ck@1140 ti,mux-clock}#ghiy@jemu_src_ckti,clkdm-gate-clock}jkpclk_fck@1140ti,divider-clock}k>y@Ipclkx2_fck@1140ti,divider-clock}k>y@Iatclk_fck@1140ti,divider-clock}k>y@Itraceclk_src_fck@1140 ti,mux-clock}#ghiy@ltraceclk_fck@1140ti,divider-clock}l >y@Isecure_32k_fck fixed-clock.mgpt12_fckfixed-factor-clock}m`kwdt1_fckfixed-factor-clock}m`ksecurity_l4_ick2fixed-factor-clock}D`knaes1_ick@a14ti,omap3-interface-clock}ny rng_ick@a14ti,omap3-interface-clock}ny sha11_ick@a14ti,omap3-interface-clock}ny des1_ick@a14ti,omap3-interface-clock}ny cam_mclk@f00ti,gate-clock}oycam_ick@f10!ti,omap3-no-wait-interface-clock}Dycsi2_96m_fck@f00ti,gate-clock}ysecurity_l3_ickfixed-factor-clock}C`kppka_ick@a14ti,omap3-interface-clock}py icr_ick@a10ti,omap3-interface-clock}Oy des2_ick@a10ti,omap3-interface-clock}Oy mspro_ick@a10ti,omap3-interface-clock}Oy mailboxes_ick@a10ti,omap3-interface-clock}Oy ssi_l4_ickfixed-factor-clock}D`kwsr1_fck@c00ti,wait-gate-clock}#y sr2_fck@c00ti,wait-gate-clock}#y sr_l4_ickfixed-factor-clock}D`kdpll2_fck@40ti,divider-clock}+>y@Iqdpll2_ck@4ti,omap3-dpll-clock}#qy$@4rdpll2_m2_ck@44ti,divider-clock}r>yDIsiva2_ck@0ti,wait-gate-clock}symodem_fck@a00ti,omap3-interface-clock}#y sad2d_ick@a10ti,omap3-interface-clock}Cy mad2d_ick@a18ti,omap3-interface-clock}Cy mspro_fck@a00ti,wait-gate-clock}y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock}$y tssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock}$y @$ussi_ssr_fck_3430es2ti,composite-clock}tuvssi_sst_fck_3430es2fixed-factor-clock}v`k hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Ny ssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}wy  usim_gate_fck@c00ti,composite-gate-clock}J y sys_d2_ckfixed-factor-clock}#`kyomap_96m_d2_fckfixed-factor-clock}J`kzomap_96m_d4_fckfixed-factor-clock}J`k{omap_96m_d8_fckfixed-factor-clock}J`k|omap_96m_d10_fckfixed-factor-clock}J`k }dpll5_m2_d4_ckfixed-factor-clock}x`k~dpll5_m2_d8_ckfixed-factor-clock}x`kdpll5_m2_d16_ckfixed-factor-clock}x`kdpll5_m2_d20_ckfixed-factor-clock}x`kusim_mux_fck@c40ti,composite-mux-clock(}#yz{|}~y @Iusim_fckti,composite-clock}usim_ick@c10ti,omap3-interface-clock}Sy  dpll5_ck@d04ti,omap3-dpll-clock}##y  $ L 4dpll5_m2_ck@d50ti,divider-clock}>y PIxsgx_gate_fck@b00ti,composite-gate-clock}+y core_d3_ckfixed-factor-clock}+`kcore_d4_ckfixed-factor-clock}+`kcore_d6_ckfixed-factor-clock}+`komap_192m_alwon_fckfixed-factor-clock}'`kcore_d2_ckfixed-factor-clock}+`ksgx_mux_fck@b40ti,composite-mux-clock }/y @sgx_fckti,composite-clock}sgx_ick@b10ti,wait-gate-clock}Cy cpefuse_fck@a08ti,gate-clock}#y ts_fck@a08ti,gate-clock}Ey usbtll_fck@a08ti,wait-gate-clock}xy usbtll_ick@a18ti,omap3-interface-clock}Oy mmchs3_ick@a10ti,omap3-interface-clock}Oy mmchs3_fck@a00ti,wait-gate-clock}y dss1_alwon_fck_3430es2@e00ti,dss-gate-clock}ydss_ick_3430es2@e10ti,omap3-dss-interface-clock}Dyusbhost_120m_fck@1400ti,gate-clock}xyusbhost_48m_fck@1400ti,dss-gate-clock}5yusbhost_ick@1410ti,omap3-dss-interface-clock}Dyclockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}kdpll4_clkdmti,clockdomain}!wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}rd2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }target-module@48320000ti,sysc-omap2ti,syscyH2H2 revsysc}Rfckick+ H2counter@0ti,omap-counter32ky interrupt-controller@48200000ti,omap3-intcyH target-module@48056000ti,sysc-omap2ti,syscyH`H`,H`(revsyscsyss#   }Nick+ H`dma-controller@0ti,omap3430-sdmati,omap-sdmay " /`gpio@48310000ti,omap3-gpioyH1gpio1<N^gpio@49050000ti,omap3-gpioyIgpio2N^en_usb2_portjsyenable usb2 portgpio@49052000ti,omap3-gpioyI gpio3N^gpio@49054000ti,omap3-gpioyI@ gpio4N^gpio@49056000ti,omap3-gpioyI`!gpio5N^gpio@49058000ti,omap3-gpioyI"gpio6N^serial@4806a000ti,omap3-uartyH HR12$txrxuart1.lserial@4806c000ti,omap3-uartyHIJ34$txrxuart2.lserial@49020000ti,omap3-uartyIJn56$txrxuart3.ladefaultoi2c@48070000 ti,omap3-i2cyH8$txrx+i2c1.'@twl@48yH  ti,twl4030adefaultortcti,twl4030-rtc bciti,twl4030-bci  vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2usb_1v8w@w@regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpioN^en_on_board_gpio_61jsyen_hsusb2_clktwl4030-usbti,twl4030-usb   pwmti,twl4030-pwm+pwmledti,twl4030-pwmled+pwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad6F8Y  7 Smadcti,twl4030-madcfpower1ti,twl4030-power-omap3-evmti,twl4030-power-idlexi2c@48072000 ti,omap3-i2cyH 9$txrx+i2c2.i2c@48060000 ti,omap3-i2cyH=$txrx+i2c3.tvp5146@5c ti,tvp5146m2y\mailbox@48094000ti,omap3-mailboxmailboxyH @dsp  spi@48098000ti,omap2-mcspiyH A+mcspi1@#$%&'()* $tx0rx0tx1rx1tx2rx2tx3rx3tsc2046@0y ti,tsc2046B@@ (-=H  Vspi@4809a000ti,omap2-mcspiyH B+mcspi2 +,-.$tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [+mcspi3 $tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiyH 0+mcspi4FG$tx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-hsmmcyH Smmc1c=>$txrxpS}adefaultommc@480b4000ti,omap3-hsmmcyH @Vmmc2/0$txrxV.}+adefaultowlcore@2 ti,wl1271yN irqwakeupImmc@480ad000ti,omap3-hsmmcyH ^mmc3MN$txrx disabledmmu@480bd400ti,omap2-iommuyH mmu_ispmmu@5d000000ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< commontxrx mcbsp1 $txrx}fck disabledtarget-module@480a0000ti,sysc-omap2ti,syscyH <H @H Drevsyscsyss}ick+ H rng@0 ti,omap2-rngy 4mcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?commontxrxsidetone mcbsp2mcbsp2_sidetone!"$txrx}fckick disabledmcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZcommontxrxsidetone mcbsp3mcbsp3_sidetone$txrx}fckick disabledmcbsp@49026000ti,omap3-mcbspyI`mpu 67 commontxrx mcbsp4$txrx}fck disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR commontxrx mcbsp5$txrx}fck disabledsham@480c3000ti,omap3-shamshamyH 0d1E$rxtarget-module@48318000ti,sysc-omap2-timerti,syscyH1H1H1revsyscsyss' }fckick+ H1)=timer@0ti,omap3430-timery}fck%HWgEtarget-module@49032000ti,sysc-omap2-timerti,syscyI I I revsyscsyss' }fckick+ I timer@0ti,omap3430-timery&timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5~timer@4903a000ti,omap3430-timeryI*timer6~timer@4903c000ti,omap3430-timeryI+timer7~timer@4903e000ti,omap3430-timeryI,timer8~timer@49040000ti,omap3430-timeryI-timer9timer@48086000ti,omap3430-timeryH`.timer10timer@48088000ti,omap3430-timeryH/timer11target-module@48304000ti,sysc-omap2-timerti,syscyH0@H0@H0@revsyscsyss' }fckick+ H0@timer@0ti,omap3430-timery_Husbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs+ ehci-phyohci@48064400ti,ohci-omap3yHDLehci@48064800 ti,ehci-omapyHHMgpmc@6e000000ti,omap3430-gpmcgpmcyn$rxtx+N^ 0,ethernet@gpmcsmsc,lan9221smsc,lan9115 %?M_q(--x+KBK\t  yadefaultonand@0,0ti,omap2-nand y micron,mt29f2g16abdhc  bch8 $?M,_,q",(6@RR(+usb_otg_hs@480ab000ti,omap3-musbyH \]mcdma usb_otg_hs 5 @ H  Q ` husb2-phy r2dss@48050000 ti,omap3-dssyHokay dss_core}fck+ x adefaulto dispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll disabled dss_dsi1} fcksys_clk+encoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpoint   ssi-controller@48058000 ti,omap3-ssissiokayyHHsysgddGgdd_mpu+ }v   ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHHtxrxCDssi-port@4805b000ti,omap3-ssi-portyHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$+&Dadefaulto pinmux_ehci_phy_pinsypinmux_hsusb2_2_pins0y   "  isp@480bc000 ti,omap3-ispyH H | l ports+bandgap@48002524yH%$ti,omap34xx-bandgap target-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreyH $sysc}fck+ H smartreflex@0ti,omap3-smartreflex-coreytarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivayH $sysc}fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivaytarget-module@50000000ti,sysc-omap2ti,syscyPrev}fckick+ P@opp-tableoperating-points-v2-ti-cpuopp1-125000000 sY@  opp2-250000000 沀 g8g8g8  opp3-500000000 e OOO opp4-550000000 U txtxtx opp5-600000000 #F ppp opp6-720000000 *T ppp  thermal-zonescpu_thermal  1 ?N  Ltripscpu_alert \8 htpassivecpu_crit \_ h tcriticalcooling-mapsmap0 s xregulator-vddvarioregulator-fixed vddvarioregulator-vdd33aregulator-fixedvdd33ahsusb2_power_regregulator-fixed hsusb2_vbus2Z2Z ^ p hsusb2_phyusb-nop-xceiv  adefaultoleds gpio-ledsledb omap3evm::ledb s default-onwl12xx_vmmcregulator-fixedvwl1271w@w@ ^ p  adefaultobacklightgpio-backlight  sregulator-lcd-3v3regulator-fixedlcd_3v32Z2Z p ^displaysharp,ls037v7dw01 lcd    $ portendpoint  memory@80000000mmemoryy compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-points-v2#cooling-cellscpu0-supplyphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsgpio-hoggpiosoutput-lowline-nameinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsti,use_poweroff#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourcependown-gpioti,dual-voltpbias-supplyvmmc-supplyvqmmc-supplybus-widthnon-removablecap-power-off-cardinterrupt-namesref-clock-frequencystatus#iommu-cellsti,#tlb-entriesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-psmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdds_dsi-supplyvdda_video-supplyremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicestartup-delay-usenable-active-highreset-gpioslabellinux,default-triggervin-supplydefault-onpower-supplyenvdd-supplyenable-gpiosmode-gpios