8( A\,timll,omap3-devkit8000ti,omap3430ti,omap3 +,7TimLL OMAP3 Devkit8000 with 7.0'' LCD panelchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/display m/connector0 v/connector1cpus+cpu@0arm,cortex-a8cpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+,Jpinmux_twl4030_pinsgApinmux_dss_dpi_pinsgscm_conf@270sysconsimple-busp0+ p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omap{pbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+mcbsp5_mux_fck@68ti,composite-mux-clockhmcbsp5_fckti,composite-clockmcbsp1_mux_fck@4ti,composite-mux-clock mcbsp1_fckti,composite-clock mcbsp2_mux_fck@4ti,composite-mux-clock  mcbsp2_fckti,composite-clock mcbsp3_mux_fck@68ti,composite-mux-clock hmcbsp3_fckti,composite-clockmcbsp4_mux_fck@68ti,composite-mux-clock hmcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+,Jpinmux_twl4030_vpins gtarget-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `Lrevsyscsyss ick+ H ` aes1@0 ti,omap3-aesP   txrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PLrevsyscsyss ick+ H P aes2@0 ti,omap3-aesP ABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockYosc_sys_ck@d40 ti,mux-clock @sys_ck@1270ti,divider-clock,p7 sys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clockNYdpll3_m2x2_ckfixed-factor-clockNYdpll4_x2_ckfixed-factor-clockNYcorex2_fckfixed-factor-clockNY!wkup_l4_ickfixed-factor-clock NYPcorex2_d3_fckfixed-factor-clock!NYcorex2_d5_fckfixed-factor-clock!NYclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockBvirt_12m_ck fixed-clockvirt_13m_ck fixed-clock]@virt_19200000_ck fixed-clock$virt_26000000_ck fixed-clockvirt_38_4m_ck fixed-clockIdpll4_ck@d00ti,omap3-dpll-per-clock  D 0dpll4_m2_ck@d48ti,divider-clock,? H7"dpll4_m2x2_mul_ckfixed-factor-clock"NY#dpll4_m2x2_ck@d00ti,gate-clock# c$omap_96m_alwon_fckfixed-factor-clock$NY+dpll3_ck@d00ti,omap3-dpll-core-clock  @ 0dpll3_m3_ck@1140ti,divider-clock,@7%dpll3_m3x2_mul_ckfixed-factor-clock%NY&dpll3_m3x2_ck@d00ti,gate-clock&  c'emu_core_alwon_ckfixed-factor-clock'NYdsys_altclk fixed-clock0mcbsp_clks fixed-clockdpll3_m2_ck@d40ti,divider-clock, @7core_ckfixed-factor-clockNY(dpll1_fck@940ti,divider-clock(, @7)dpll1_ck@904ti,omap3-dpll-clock )  $ @ 4dpll1_x2_ckfixed-factor-clockNY*dpll1_x2m2_ck@944ti,divider-clock*, D7>cm_96m_fckfixed-factor-clock+NY,omap_96m_fck@d40 ti,mux-clock,  @Gdpll4_m3_ck@e40ti,divider-clock, @7-dpll4_m3x2_mul_ckfixed-factor-clock-NY.dpll4_m3x2_ck@d00ti,gate-clock. c/omap_54m_fck@d40 ti,mux-clock/0 @:cm_96m_d2_fckfixed-factor-clock,NY1omap_48m_fck@d40 ti,mux-clock10 @2omap_12m_fckfixed-factor-clock2NYIdpll4_m4_ck@e40ti,divider-clock,@73dpll4_m4x2_mul_ckti,fixed-factor-clock3y4dpll4_m4x2_ck@d00ti,gate-clock4 cdpll4_m5_ck@f40ti,divider-clock,?@75dpll4_m5x2_mul_ckti,fixed-factor-clock5y6dpll4_m5x2_ck@d00ti,gate-clock6 cldpll4_m6_ck@1140ti,divider-clock,?@77dpll4_m6x2_mul_ckfixed-factor-clock7NY8dpll4_m6x2_ck@d00ti,gate-clock8 c9emu_per_alwon_ckfixed-factor-clock9NYeclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock( p;clkout2_src_mux_ck@d70ti,composite-mux-clock( ,: p<clkout2_src_ckti,composite-clock;<=sys_clkout2@d70ti,divider-clock=,@ pmpu_ckfixed-factor-clock>NY?arm_fck@924ti,divider-clock? $,emu_mpu_alwon_ckfixed-factor-clock?NYfl3_ick@a40ti,divider-clock(, @7@l4_ick@a40ti,divider-clock@, @7Arm_ick@c40ti,divider-clockA, @7gpt10_gate_fck@a00ti,composite-gate-clock   Cgpt10_mux_fck@a40ti,composite-mux-clockB  @Dgpt10_fckti,composite-clockCDgpt11_gate_fck@a00ti,composite-gate-clock   Egpt11_mux_fck@a40ti,composite-mux-clockB  @Fgpt11_fckti,composite-clockEFcore_96m_fckfixed-factor-clockGNYmmchs2_fck@a00ti,wait-gate-clock mmchs1_fck@a00ti,wait-gate-clock i2c3_fck@a00ti,wait-gate-clock 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@agpt9_fckti,composite-clock`aper_32k_alwon_fckfixed-factor-clockBNYbgpio6_dbck@1000ti,gate-clockbgpio5_dbck@1000ti,gate-clockbgpio4_dbck@1000ti,gate-clockbgpio3_dbck@1000ti,gate-clockbgpio2_dbck@1000ti,gate-clockb wdt3_fck@1000ti,wait-gate-clockb per_l4_ickfixed-factor-clockANYcgpio6_ick@1010ti,omap3-interface-clockcgpio5_ick@1010ti,omap3-interface-clockcgpio4_ick@1010ti,omap3-interface-clockcgpio3_ick@1010ti,omap3-interface-clockcgpio2_ick@1010ti,omap3-interface-clockc wdt3_ick@1010ti,omap3-interface-clockc uart3_ick@1010ti,omap3-interface-clockc uart4_ick@1010ti,omap3-interface-clockcgpt9_ick@1010ti,omap3-interface-clockc gpt8_ick@1010ti,omap3-interface-clockc gpt7_ick@1010ti,omap3-interface-clockcgpt6_ick@1010ti,omap3-interface-clockcgpt5_ick@1010ti,omap3-interface-clockcgpt4_ick@1010ti,omap3-interface-clockcgpt3_ick@1010ti,omap3-interface-clockcgpt2_ick@1010ti,omap3-interface-clockcmcbsp2_ick@1010ti,omap3-interface-clockcmcbsp3_ick@1010ti,omap3-interface-clockcmcbsp4_ick@1010ti,omap3-interface-clockcmcbsp2_gate_fck@1000ti,composite-gate-clock mcbsp3_gate_fck@1000ti,composite-gate-clockmcbsp4_gate_fck@1000ti,composite-gate-clockemu_src_mux_ck@1140 ti,mux-clock def@gemu_src_ckti,clkdm-gate-clockghpclk_fck@1140ti,divider-clockh,@7pclkx2_fck@1140ti,divider-clockh,@7atclk_fck@1140ti,divider-clockh,@7traceclk_src_fck@1140 ti,mux-clock def@itraceclk_fck@1140ti,divider-clocki ,@7secure_32k_fck fixed-clockjgpt12_fckfixed-factor-clockjNYwdt1_fckfixed-factor-clockjNYsecurity_l4_ick2fixed-factor-clockANYkaes1_ick@a14ti,omap3-interface-clockk rng_ick@a14ti,omap3-interface-clockk sha11_ick@a14ti,omap3-interface-clockk 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2AT0W6ve6gsZZusb_otg_hs@480ab000ti,omap3-musbH \]mcdma usb_otg_hs dss@48050000 ti,omap3-dssHSokay dss_corefck+ldefaultz  dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll Sdisabled dss_dsi1 fcksys_clk+encoder@48050800ti,omap3-rfbiH Sdisabled dss_rfbifckickencoder@48050c00ti,omap3-vencH Sokay dss_vencfck )portendpoint 5 Eport+endpoint@0 5 Q endpoint@1 5 Qssi-controller@48058000 ti,omap3-ssissiSokayHHsysgddGgdd_mpu+ s ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+,Jisp@480bc000 ti,omap3-ispH H | \{l cports+bandgap@48002524H%$ti,omap34xx-bandgap otarget-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreH $syscfck+ H smartreflex@0ti,omap3-smartreflex-coretarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivaH $syscfck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivatarget-module@50000000ti,sysc-omap2ti,syscPrevfckick+ P@opp-tableoperating-points-v2-ti-cpu{opp1-125000000 sY@  opp2-250000000 沀 g8g8g8  opp3-500000000 e OOO opp4-550000000 U txtxtx opp5-600000000 #F ppp opp6-720000000 *T ppp  thermal-zonescpu_thermal   N  tripscpu_alert 8 passivecpu_crit _  criticalcooling-mapsmap0  memory@80000000memoryleds gpio-ledsheartbeatdevkit8000::led1 . 4on Bheartbeatmmcdevkit8000::led2 . 4on Bnoneusrdevkit8000::led3 . 4on Busrpmu_statdevkit8000::pmu_stat . soundti,omap-twl4030 Xdevkit8000 a I jExt SpkPREDRIVELExt SpkPREDRIVERMAINMICMain MicMain MicMic Bias 1gpio_keys gpio-keysuseruser . {qencoder0 ti,tfp410  ports+port@0endpoint 5 port@1endpoint 5 connector0dvi-connectordvi   portendpoint 5 connector1svideo-connectortvportendpoint 5display panel-dpilcd  portendpoint 5panel-timingbZ      0      ' 1 compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0display1display2device_typeregclocksclock-namesclock-latencyoperating-points-v2#cooling-cellsphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyio-channelsio-channel-namesti,use-ledsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsstatus#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repti,keep-vref-onti,settle-delay-usecwakeup-sourceti,dual-voltpbias-supplyvmmc-supplyvqmmc-supplybus-width#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthdavicom,no-eepromgpmc,mux-add-datagpmc,wait-pingpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsmultipointnum-epsram-bitsvdds_dsi-supplyvdda_dac-supplyvdda-supplyremote-endpointti,channelsdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicegpiosdefault-statelinux,default-triggerti,modelti,mcbspti,audio-routinglinux,codepowerdown-gpiosdigitalddc-i2c-busenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-active