ݥ8(+compulab,omap3-cm-t3517ti,am3517ti,omap3 +7CompuLab CM-T3517chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@4809e000l/ocp@68000000/can@5c050000cpus+cpu@0arm,cortex-a8pcpu|cpupmu@54000000arm,cortex-a8-pmu|Tdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus|h +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus| + pinmux@30 ti,omap3-padconfpinctrl-single|08+ +pinmux_uart3_pinsHnp\pinmux_mmc1_pins0H\pinmux_green_led_pinsH\pinmux_dss_dpi_pins_commonH\pinmux_dss_dpi_pins_cm_t35x0H\pinmux_ads7846_pinsH\pinmux_mcspi1_pins H\pinmux_i2c1_pinsH\pinmux_mcbsp2_pins H \pinmux_hsusb1_phy_reset_pinsHH\pinmux_hsusb2_phy_reset_pinsHJ\pinmux_otg_drv_vbusH\pinmux_mmc2_pins0H(*,.02\pinmux_wl12xx_core_pinsHF\pinmux_usb_hub_pinsHTscm_conf@270sysconsimple-bus|p0+ p0\pbias_regulator@2b0ti,pbias-omap3ti,pbias-omap|dpbias_mmc_omap2430kpbias_mmc_omap2430zw@-\clocks+mcbsp5_mux_fck@68ti,composite-mux-clock|h\mcbsp5_fckti,composite-clock\mcbsp1_mux_fck@4ti,composite-mux-clock|\ mcbsp1_fckti,composite-clock \mcbsp2_mux_fck@4ti,composite-mux-clock |\ mcbsp2_fckti,composite-clock \mcbsp3_mux_fck@68ti,composite-mux-clock |h\mcbsp3_fckti,composite-clock\mcbsp4_mux_fck@68ti,composite-mux-clock |h\mcbsp4_fckti,composite-clock\emac_ick@32cti,am35xx-gate-clock|,\xemac_fck@32cti,gate-clock|, \vpfe_ick@32cti,am35xx-gate-clock|,\yvpfe_fck@32cti,gate-clock|, hsotgusb_ick_am35xx@32cti,am35xx-gate-clock|,\zhsotgusb_fck_am35xx@32cti,gate-clock|,\{hecc_ck@32cti,am35xx-gate-clock|,\|clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single| \+ +pinmux_wl12xx_wkup_pinsH\prm@48306000 ti,omap3-prm|H0`@ clocks+virt_16_8m_ck fixed-clockY\osc_sys_ck@d40 ti,mux-clock| @\sys_ck@1270ti,divider-clock|p\sys_clkout1@d70ti,gate-clock| pdpll3_x2_ckfixed-factor-clockdpll3_m2x2_ckfixed-factor-clock\ dpll4_x2_ckfixed-factor-clockcorex2_fckfixed-factor-clock \!wkup_l4_ickfixed-factor-clock\Pcorex2_d3_fckfixed-factor-clock!\qcorex2_d5_fckfixed-factor-clock!\rclockdomainscm@48004000 ti,omap3-cm|H@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock\Bvirt_12m_ck fixed-clock\virt_13m_ck fixed-clock]@\virt_19200000_ck fixed-clock$\virt_26000000_ck fixed-clock\virt_38_4m_ck fixed-clockI\dpll4_ck@d00ti,omap3-dpll-per-clock| D 0\dpll4_m2_ck@d48ti,divider-clock?| H\"dpll4_m2x2_mul_ckfixed-factor-clock"\#dpll4_m2x2_ck@d00ti,gate-clock#|  \$omap_96m_alwon_fckfixed-factor-clock$\+dpll3_ck@d00ti,omap3-dpll-core-clock| @ 0\dpll3_m3_ck@1140ti,divider-clock|@\%dpll3_m3x2_mul_ckfixed-factor-clock%\&dpll3_m3x2_ck@d00ti,gate-clock& |  \'emu_core_alwon_ckfixed-factor-clock'\dsys_altclk fixed-clock\0mcbsp_clks fixed-clock\dpll3_m2_ck@d40ti,divider-clock| @\core_ckfixed-factor-clock\(dpll1_fck@940ti,divider-clock(| @\)dpll1_ck@904ti,omap3-dpll-clock)|  $ @ 4\dpll1_x2_ckfixed-factor-clock\*dpll1_x2m2_ck@944ti,divider-clock*| D\>cm_96m_fckfixed-factor-clock+\,omap_96m_fck@d40 ti,mux-clock,| @\Gdpll4_m3_ck@e40ti,divider-clock |@\-dpll4_m3x2_mul_ckfixed-factor-clock-\.dpll4_m3x2_ck@d00ti,gate-clock.|  \/omap_54m_fck@d40 ti,mux-clock/0| @\:cm_96m_d2_fckfixed-factor-clock,\1omap_48m_fck@d40 ti,mux-clock10| @\2omap_12m_fckfixed-factor-clock2\Idpll4_m4_ck@e40ti,divider-clock|@\3dpll4_m4x2_mul_ckti,fixed-factor-clock3!/<\4dpll4_m4x2_ck@d00ti,gate-clock4|  <\vdpll4_m5_ck@f40ti,divider-clock?|@\5dpll4_m5x2_mul_ckti,fixed-factor-clock5!/<\6dpll4_m5x2_ck@d00ti,gate-clock6|  <dpll4_m6_ck@1140ti,divider-clock?|@\7dpll4_m6x2_mul_ckfixed-factor-clock7\8dpll4_m6x2_ck@d00ti,gate-clock8|  \9emu_per_alwon_ckfixed-factor-clock9\eclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock(| p\;clkout2_src_mux_ck@d70ti,composite-mux-clock(,:| p\<clkout2_src_ckti,composite-clock;<\=sys_clkout2@d70ti,divider-clock=@| pOmpu_ckfixed-factor-clock>\?arm_fck@924ti,divider-clock?| $emu_mpu_alwon_ckfixed-factor-clock?\fl3_ick@a40ti,divider-clock(| @\@l4_ick@a40ti,divider-clock@| @\Arm_ick@c40ti,divider-clockA| @gpt10_gate_fck@a00ti,composite-gate-clock | \Cgpt10_mux_fck@a40ti,composite-mux-clockB| @\Dgpt10_fckti,composite-clockCDgpt11_gate_fck@a00ti,composite-gate-clock | \Egpt11_mux_fck@a40ti,composite-mux-clockB| @\Fgpt11_fckti,composite-clockEFcore_96m_fckfixed-factor-clockG\mmchs2_fck@a00ti,wait-gate-clock| \mmchs1_fck@a00ti,wait-gate-clock| \i2c3_fck@a00ti,wait-gate-clock| \i2c2_fck@a00ti,wait-gate-clock| \i2c1_fck@a00ti,wait-gate-clock| \mcbsp5_gate_fck@a00ti,composite-gate-clock | \mcbsp1_gate_fck@a00ti,composite-gate-clock | \ core_48m_fckfixed-factor-clock2\Hmcspi4_fck@a00ti,wait-gate-clockH| \mcspi3_fck@a00ti,wait-gate-clockH| \mcspi2_fck@a00ti,wait-gate-clockH| \mcspi1_fck@a00ti,wait-gate-clockH| \uart2_fck@a00ti,wait-gate-clockH| \uart1_fck@a00ti,wait-gate-clockH|  \core_12m_fckfixed-factor-clockI\Jhdq_fck@a00ti,wait-gate-clockJ| \core_l3_ickfixed-factor-clock@\Ksdrc_ick@a10ti,wait-gate-clockK| \wgpmc_fckfixed-factor-clockKcore_l4_ickfixed-factor-clockA\Lmmchs2_ick@a10ti,omap3-interface-clockL| \mmchs1_ick@a10ti,omap3-interface-clockL| \hdq_ick@a10ti,omap3-interface-clockL| \mcspi4_ick@a10ti,omap3-interface-clockL| \mcspi3_ick@a10ti,omap3-interface-clockL| \mcspi2_ick@a10ti,omap3-interface-clockL| \mcspi1_ick@a10ti,omap3-interface-clockL| \i2c3_ick@a10ti,omap3-interface-clockL| \i2c2_ick@a10ti,omap3-interface-clockL| \i2c1_ick@a10ti,omap3-interface-clockL| \uart2_ick@a10ti,omap3-interface-clockL| \uart1_ick@a10ti,omap3-interface-clockL|  \gpt11_ick@a10ti,omap3-interface-clockL|  \gpt10_ick@a10ti,omap3-interface-clockL|  \mcbsp5_ick@a10ti,omap3-interface-clockL|  \mcbsp1_ick@a10ti,omap3-interface-clockL|  \omapctrl_ick@a10ti,omap3-interface-clockL| \dss_tv_fck@e00ti,gate-clock:|\dss_96m_fck@e00ti,gate-clockG|\dss2_alwon_fck@e00ti,gate-clock|\dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock| \Mgpt1_mux_fck@c40ti,composite-mux-clockB| @\Ngpt1_fckti,composite-clockMN\aes2_ick@a10ti,omap3-interface-clockL| \wkup_32k_fckfixed-factor-clockB\Ogpio1_dbck@c00ti,gate-clockO| \sha12_ick@a10ti,omap3-interface-clockL| \wdt2_fck@c00ti,wait-gate-clockO| \wdt2_ick@c10ti,omap3-interface-clockP| \wdt1_ick@c10ti,omap3-interface-clockP| \gpio1_ick@c10ti,omap3-interface-clockP| \omap_32ksync_ick@c10ti,omap3-interface-clockP| \gpt12_ick@c10ti,omap3-interface-clockP| \gpt1_ick@c10ti,omap3-interface-clockP| \per_96m_fckfixed-factor-clock+\ per_48m_fckfixed-factor-clock2\Quart3_fck@1000ti,wait-gate-clockQ| \}gpt2_gate_fck@1000ti,composite-gate-clock|\Rgpt2_mux_fck@1040ti,composite-mux-clockB|@\Sgpt2_fckti,composite-clockRS\gpt3_gate_fck@1000ti,composite-gate-clock|\Tgpt3_mux_fck@1040ti,composite-mux-clockB|@\Ugpt3_fckti,composite-clockTUgpt4_gate_fck@1000ti,composite-gate-clock|\Vgpt4_mux_fck@1040ti,composite-mux-clockB|@\Wgpt4_fckti,composite-clockVWgpt5_gate_fck@1000ti,composite-gate-clock|\Xgpt5_mux_fck@1040ti,composite-mux-clockB|@\Ygpt5_fckti,composite-clockXYgpt6_gate_fck@1000ti,composite-gate-clock|\Zgpt6_mux_fck@1040ti,composite-mux-clockB|@\[gpt6_fckti,composite-clockZ[gpt7_gate_fck@1000ti,composite-gate-clock|\\gpt7_mux_fck@1040ti,composite-mux-clockB|@\]gpt7_fckti,composite-clock\]gpt8_gate_fck@1000ti,composite-gate-clock |\^gpt8_mux_fck@1040ti,composite-mux-clockB|@\_gpt8_fckti,composite-clock^_gpt9_gate_fck@1000ti,composite-gate-clock |\`gpt9_mux_fck@1040ti,composite-mux-clockB|@\agpt9_fckti,composite-clock`aper_32k_alwon_fckfixed-factor-clockB\bgpio6_dbck@1000ti,gate-clockb|\~gpio5_dbck@1000ti,gate-clockb|\gpio4_dbck@1000ti,gate-clockb|\gpio3_dbck@1000ti,gate-clockb|\gpio2_dbck@1000ti,gate-clockb| \wdt3_fck@1000ti,wait-gate-clockb| \per_l4_ickfixed-factor-clockA\cgpio6_ick@1010ti,omap3-interface-clockc|\gpio5_ick@1010ti,omap3-interface-clockc|\gpio4_ick@1010ti,omap3-interface-clockc|\gpio3_ick@1010ti,omap3-interface-clockc|\gpio2_ick@1010ti,omap3-interface-clockc| \wdt3_ick@1010ti,omap3-interface-clockc| \uart3_ick@1010ti,omap3-interface-clockc| \uart4_ick@1010ti,omap3-interface-clockc|\gpt9_ick@1010ti,omap3-interface-clockc| \gpt8_ick@1010ti,omap3-interface-clockc| \gpt7_ick@1010ti,omap3-interface-clockc|\gpt6_ick@1010ti,omap3-interface-clockc|\gpt5_ick@1010ti,omap3-interface-clockc|\gpt4_ick@1010ti,omap3-interface-clockc|\gpt3_ick@1010ti,omap3-interface-clockc|\gpt2_ick@1010ti,omap3-interface-clockc|\mcbsp2_ick@1010ti,omap3-interface-clockc|\mcbsp3_ick@1010ti,omap3-interface-clockc|\mcbsp4_ick@1010ti,omap3-interface-clockc|\mcbsp2_gate_fck@1000ti,composite-gate-clock|\ mcbsp3_gate_fck@1000ti,composite-gate-clock|\mcbsp4_gate_fck@1000ti,composite-gate-clock|\emu_src_mux_ck@1140 ti,mux-clockdef|@\gemu_src_ckti,clkdm-gate-clockg\hpclk_fck@1140ti,divider-clockh|@pclkx2_fck@1140ti,divider-clockh|@atclk_fck@1140ti,divider-clockh|@traceclk_src_fck@1140 ti,mux-clockdef|@\itraceclk_fck@1140ti,divider-clocki |@secure_32k_fck fixed-clock\jgpt12_fckfixed-factor-clockj\wdt1_fckfixed-factor-clockjipss_ick@a10ti,am35xx-interface-clockK| \rmii_ck fixed-clock\pclk_ck fixed-clock\uart4_ick_am35xx@a10ti,omap3-interface-clockL| uart4_fck_am35xx@a00ti,wait-gate-clockH| dpll5_ck@d04ti,omap3-dpll-clock|  $ L 4ew\kdpll5_m2_ck@d50ti,divider-clockk| P\usgx_gate_fck@b00ti,composite-gate-clock(| \score_d3_ckfixed-factor-clock(\lcore_d4_ckfixed-factor-clock(\mcore_d6_ckfixed-factor-clock(\nomap_192m_alwon_fckfixed-factor-clock$\ocore_d2_ckfixed-factor-clock(\psgx_mux_fck@b40ti,composite-mux-clock lmn,opqr| @\tsgx_fckti,composite-clockst\sgx_ick@b10ti,wait-gate-clock@| \cpefuse_fck@a08ti,gate-clock| \ts_fck@a08ti,gate-clockB| \usbtll_fck@a08ti,wait-gate-clocku| \usbtll_ick@a18ti,omap3-interface-clockL| \mmchs3_ick@a10ti,omap3-interface-clockL| \mmchs3_fck@a00ti,wait-gate-clock| \dss1_alwon_fck_3430es2@e00ti,dss-gate-clockv|<\dss_ick_3430es2@e10ti,omap3-dss-interface-clockA|\usbhost_120m_fck@1400ti,gate-clocku|\usbhost_48m_fck@1400ti,dss-gate-clock2|\usbhost_ick@1410ti,omap3-dss-interface-clockA|\clockdomainscore_l3_clkdmti,clockdomainwxyz{|dpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainh}~emu_clkdmti,clockdomainhdpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaindpll5_clkdmti,clockdomainksgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain target-module@48320000ti,sysc-omap2ti,sysc|H2H2 revsyscOfckick+ H2counter@0ti,omap-counter32k| interrupt-controller@48200000ti,omap3-intc|H \target-module@48056000ti,sysc-omap2ti,sysc|H`H`,H`(revsyscsyss#  Kick+ H`dma-controller@0ti,omap3430-sdmati,omap-sdma|  `\gpio@48310000ti,omap3-gpio|H1gpio1\gpio@49050000ti,omap3-gpio|Igpio2\gpio@49052000ti,omap3-gpio|I gpio3gpio@49054000ti,omap3-gpio|I@ gpio4gpio@49056000ti,omap3-gpio|I`!gpio5\gpio@49058000ti,omap3-gpio|I"gpio6\serial@4806a000ti,omap3-uart|H H&12+txrxuart1lserial@4806c000ti,omap3-uart|HI&34+txrxuart2lserial@49020000ti,omap3-uart|IJ&56+txrxuart3l5defaultCi2c@48070000 ti,omap3-i2c|H8&+txrx+i2c15defaultCat24@50 atmel,24c02M|Pi2c@48072000 ti,omap3-i2c|H 9&+txrx+i2c2i2c@48060000 ti,omap3-i2c|H=&+txrx+i2c3mailbox@48094000ti,omap3-mailboxmailbox|H @Vbt disableddsp  spi@48098000ti,omap2-mcspi|H A+mcspi1@&#$%&'()* +tx0rx0tx1rx1tx2rx2tx3rx35defaultCads7846@05defaultC ti,ads7846|`  ( 8Hspi@4809a000ti,omap2-mcspi|H B+mcspi2 &+,-.+tx0rx0tx1rx1spi@480b8000ti,omap2-mcspi|H [+mcspi3 &+tx0rx0tx1rx1spi@480ba000ti,omap2-mcspi|H 0+mcspi4&FG+tx0rx01w@480b2000 ti,omap3-1w|H :hdq1wmmc@4809c000ti,omap3-hsmmc|H Smmc1V&=>+txrxc5defaultCpzmmc@480b4000ti,omap3-hsmmc|H @Vmmc2&/0+txrx5defaultCzp+wlcore@2 ti,wl1271| Immc@480ad000ti,omap3-hsmmc|H ^mmc3&MN+txrx disabledmmu@480bd400ti,omap2-iommu|H mmu_isp disabledmmu@5d000000ti,omap2-iommu|]mmu_iva disabledwdt@48314000 ti,omap3-wdt|H1@ wd_timer2mcbsp@48074000ti,omap3-mcbsp|H@mpu ;< commontxrxmcbsp1& +txrxfck disabledtarget-module@480a0000ti,sysc-omap2ti,sysc|H <H @H Drevsyscsyssick+ H  disabledrng@0 ti,omap2-rng| 4mcbsp@49022000ti,omap3-mcbsp|I I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone&!"+txrxfckickokay5defaultCmcbsp@49024000ti,omap3-mcbsp|I@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetone&+txrxfckick disabledmcbsp@49026000ti,omap3-mcbsp|I`mpu 67 commontxrxmcbsp4&+txrxfck disabledmcbsp@48096000ti,omap3-mcbsp|H `mpu QR commontxrxmcbsp5&+txrxfck disabledsham@480c3000ti,omap3-shamsham|H 0d1&E+rxtarget-module@48318000ti,sysc-omap2-timerti,sysc|H1H1H1revsyscsyss' fckick+ H1)timer@0ti,omap3430-timer|fck%4CStarget-module@49032000ti,sysc-omap2-timerti,sysc|I I I revsyscsyss' fckick+ I )timer@0ti,omap3430-timer|&CStimer@49034000ti,omap3430-timer|I@'timer3timer@49036000ti,omap3430-timer|I`(timer4timer@49038000ti,omap3430-timer|I)timer5jtimer@4903a000ti,omap3430-timer|I*timer6jtimer@4903c000ti,omap3430-timer|I+timer7jtimer@4903e000ti,omap3430-timer|I,timer8wjtimer@49040000ti,omap3430-timer|I-timer9wtimer@48086000ti,omap3430-timer|H`.timer10wtimer@48088000ti,omap3430-timer|H/timer11wtarget-module@48304000ti,sysc-omap2-timerti,sysc|H0@H0@H0@revsyscsyss' fckick+ H0@timer@0ti,omap3430-timer|_4usbhstll@48062000 ti,usbhs-tll|H N usb_tll_hsusbhshost@48064000ti,usbhs-host|H@ usb_host_hs+ ehci-phy ehci-phyohci@48064400ti,ohci-omap3|HDLehci@48064800 ti,ehci-omap|HHMgpmc@6e000000ti,omap3430-gpmcgpmc|n&+rxtx+0\nand@0,0ti,omap2-nand | sw$x6xHWxjx}ZZH<x x.Z+partition@0Fxloader|partition@80000Fuboot|partition@260000Fuboot environment|&partition@2a0000Flinux|*@partition@6a0000Frootfs|jusb_otg_hs@480ab000ti,omap3-musb|H \]mcdma usb_otg_hsLW_  disableddss@48050000 ti,omap3-dss|Hokay dss_corefck+5defaultCdispc@48050400ti,omap3-dispc|H dss_dispcfckencoder@4804fc00 ti,omap3-dsi|HH@H protophypll disabled dss_dsi1 fcksys_clk+encoder@48050800ti,omap3-rfbi|H disabled dss_rfbifckickencoder@48050c00ti,omap3-venc|H okay dss_vencfckportendpointhx\ssi-controller@48058000 ti,omap3-ssissi disabled|HHsysgddGgdd_mpu+ssi-port@4805a000ti,omap3-ssi-port|HHtxrxCDssi-port@4805b000ti,omap3-ssi-port|HHtxrxEFam35x_otg_hs@5c040000ti,omap3-musb am35x_otg_hsokay|\Gmc5defaultCethernet@5c000000ti,am3517-emac davinci_emacokay|\CDEFd xickmdio@5c030000ti,davinci_mdio davinci_mdiookay|\B@+fckserial@4809e000ti,omap3-uartuart4 disabled|H T&76+txrxlpinmux@480025d8 ti,omap3-padconfpinctrl-single|H%$+ +can@5c050000ti,am3517-hecc disabled|\\0\ hecchecc-rammbx|target-module@50000000ti,sysc-omap2ti,sysc|Prevfckick+ P@opp-tableoperating-points-v2-ti-cpud\opp50-300000000 'O5Fopp100-600000000 #F'O5memory@80000000pmemory|leds gpio-leds5defaultCledb Fcm-t3x:green R Xheartbeathsusb1_power_regregulator-fixed khsusb1_vbusz2Z2Znp\hsusb2_power_regregulator-fixed khsusb2_vbusz2Z2Znp\hsusb1_phyusb-nop-xceiv5defaultC \hsusb2_phyusb-nop-xceiv5defaultC \ads7846-regregulator-fixed kads7846-regz2Z2Z\svideo-connectorsvideo-connectorFtvportendpointh\regulator-vmmcregulator-fixedkvmmcz2Z2Z\wl12xx_vmmc2regulator-fixedkvw12715defaultCzw@w@ nN \wl12xx_vaux2regulator-fixedkvwl1271_vaux2zw@w@\ compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3candevice_typeregclocksclock-namesclock-latencyoperating-points-v2interruptsti,hwmodsstatusranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockreg-namesti,sysc-sidleti,sysc-maskti,sysc-midleti,syss-mask#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendeddmasdma-namespinctrl-namespinctrl-0pagesize#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repwakeup-sourceti,dual-voltpbias-supplybus-widthvmmc-supplyvqmmc-supplynon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,page-burst-access-nsgpmc,access-nsgpmc,cycle2cycle-delay-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelmultipointnum-epsram-bitsremote-endpointti,channelsti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freqopp-hzopp-microvoltopp-supported-hwopp-suspendgpioslinux,default-triggerstartup-delay-us#phy-cellsreset-gpiosenable-active-high