^8Z(6ZX #,WITS A31 Colombus Evaluation Board"2wits,colombusallwinner,sun6i-a31aliases=/soc/ethernet@1c30000G/soc/serial@1c28000chosen OVserial0:115200n8framebuffer-lcd0-hdmi02allwinner,simple-framebuffersimple-framebufferbde_be0-lcd0-hdmi@u3/2wz |disabledframebuffer-lcd002allwinner,simple-framebuffersimple-framebuffer bde_be0-lcd00u3/wz |disabledtimer2arm,armv7-timer0   n6cpusallwinner,sun6i-a31 cpu@02arm,cortex-a7cpuu aO /O SB@cpu@12arm,cortex-a7cpuu aO /O SB@cpu@22arm,cortex-a7cpuu aO /O SB@cpu@32arm,cortex-a7cpuu aO /O SB@thermal-zonescpu_thermal,:cooling-mapsmap0J0Otripscpu_alert0^pjpassivecpu_crit^j criticalpmu2arm,cortex-a7-pmu0xyz{clocks Oclk-24Mu 2fixed-clockn6osc24Mclk-32ku 2fixed-clockosc32kclk-mii-phy-txu 2fixed-clock}x@ mii_phy_tx clk-gmac-int-txu 2fixed-clocksY@ gmac_int_tx clk@1c200d0u2allwinner,sun7i-a20-gmac-clku gmac_tx"display-engine#2allwinner,sun6i-a31-display-engine  |disabledsoc 2simple-bus Odma-controller@1c020002allwinner,sun6i-a31-dma  2ulcd-controller@1c0c0002allwinner,sun6i-a31-tcon Vlcdu/ahbtcon-ch0tcon-ch1tcon0-pixel-clockports port@0 endpoint@0 3endpoint@1-port@1 endpoint@1lcd-controller@1c0d0002allwinner,sun6i-a31-tcon Wlcdu0ahbtcon-ch0tcon-ch1tcon1-pixel-clockports port@0 endpoint@04endpoint@1.port@1 endpoint@1mmc@1c0f0002allwinner,sun7i-a20-mmc uOQPahbmmcoutputsampleahb <default|okay (mmc@1c100002allwinner,sun7i-a20-mmc uRTSahbmmcoutputsampleahb =default |disabled mmc@1c110002allwinner,sun7i-a20-mmc uUWVahbmmcoutputsampleahb > |disabled mmc@1c120002allwinner,sun7i-a20-mmc  uXZYahbmmcoutputsample ahb ? |disabled hdmi@1c160002allwinner,sun6i-a31-hdmi` X(u2 ahbmodddcpll-0pll-1ahb1ddc-txddc-rxaudio-tx;   |disabledports port@0 endpoint@0endpoint@1port@1 usb@1c190002allwinner,sun6i-a31-musbu( G@mcPUusb_ |disabledphy@1c194002allwinner,sun6i-a31-usb-phyfphy_ctrlpmu1pmu2udefusb0_phyusb1_phyusb2_phy!usb0_resetusb1_resetusb2_reset|okayp{usb@1c1a000&2allwinner,sun6i-a31-ehcigeneric-ehci Hu)PUusb |disabledusb@1c1a400&2allwinner,sun6i-a31-ohcigeneric-ohci Iu+gPUusb |disabledusb@1c1b000&2allwinner,sun6i-a31-ehcigeneric-ehci Ju*PUusb|okayusb@1c1b400&2allwinner,sun6i-a31-ohcigeneric-ohci Ku,hPUusb |disabledusb@1c1c400&2allwinner,sun6i-a31-ohcigeneric-ohci Mu-i |disabledclock@1c200002allwinner,sun6i-a31-ccuu hoscloscupinctrl@1c208002allwinner,sun6i-a31-pinctrl0 u@apbhoscloscgmac-gmii-pinsPA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27gmacgmac-mii-pinsTPA0PA1PA2PA3PA8PA9PA11PA12PA13PA14PA19PA20PA21PA22PA23PA24PA26PA27gmacgmac-rgmii-pinsFPA0PA1PA2PA3PA9PA10PA11PA12PA13PA14PA19PA20PA25PA26PA27gmac(#i2c0-pins PH14PH15i2c0i2c1-pins PH16PH17i2c1 i2c2-pins PH18PH19i2c2!lcd0-rgb888-pinsPD0PD1PD2PD3PD4PD5PD6PD7PD8PD9PD10PD11PD12PD13PD14PD15PD16PD17PD18PD19PD20PD21PD22PD23PD24PD25PD26PD27lcd0mmc0-pinsPF0PF1PF2PF3PF4PF5mmc0mmc1-pinsPG0PG1PG2PG3PG4PG5mmc1mmc2-4bit-pinsPC6PC7PC8PC9PC10PC11mmc2mmc2-8bit-emmc-pins3PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC24mmc2mmc3-8bit-emmc-pins3PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC24mmc3(spdif-tx-pinPH28spdifuart0-ph-pins PH20PH21uart0i2c-lcd-pins PA23PA24 gpio_out<timer@1c20c002allwinner,sun4i-a10-timer <uwatchdog@1c20ca02allwinner,sun6i-a31-wdt spdif@1c210002allwinner,sun6i-a31-spdif u>c+ apbspdif;1rxtx |disabledi2s@1c220002allwinner,sun6i-a31-i2s  uAa-apbmod;1rxtx |disabledi2s@1c224002allwinner,sun6i-a31-i2s$ uBb.apbmod;1rxtx |disabledlradc@1c228002allwinner,sun4i-a10-lradc-keys(  |disabledrtp@1c250002allwinner,sun6i-a31-tsP serial@1c280002snps,dw-apb-uart€ ,6uG3;1rxtx|okaydefaultserial@1c284002snps,dw-apb-uart„ ,6uH4;1rxtx |disabledserial@1c288002snps,dw-apb-uartˆ ,6uI5;1rxtx |disabledserial@1c28c002snps,dw-apb-uartŒ ,6uJ6;  1rxtx |disabledserial@1c290002snps,dw-apb-uart ,6uK7;  1rxtx |disabledserial@1c294002snps,dw-apb-uart” ,6uL8;1rxtx |disabledi2c@1c2ac002allwinner,sun6i-a31-i2c¬ uC/default|fail i2c@1c2b0002allwinner,sun6i-a31-i2c° uD0default |okay i2c@1c2b4002allwinner,sun6i-a31-i2c´ uE1default!|okay mma8452@1d 2fsl,mma8452 i2c@1c2b8002allwinner,sun6i-a31-i2c¸ uF2 |disabled ethernet@1c300002allwinner,sun7i-a20-gmacT R@macirq u!"stmmacethallwinner_gmac_tx  stmmacethCL]|okay default#t$xrgmiiethernet-phy@1$crypto-engine@1c1500062allwinner,sun6i-a31-cryptoallwinner,sun4i-a10-cryptoP Pu\ahbmodahbcodec@1c22c002allwinner,sun6i-a31-codec, u= apbcodec*;1rxtx |disabledtimer@1c6000082allwinner,sun6i-a31-hstimerallwinner,sun7i-a20-hstimer03456u#spi@1c680002allwinner,sun6i-a31-spiƀ Au$]ahbmod;1rxtx |disabledspi@1c690002allwinner,sun6i-a31-spiƐ Bu%^ahbmod;1rxtx |disabledspi@1c6a0002allwinner,sun6i-a31-spiƠ Cu&_ahbmod;1rxtx |disabledspi@1c6b0002allwinner,sun6i-a31-spiư Du'`ahbmod;1rxtx |disabledinterrupt-controller@1c81000%2arm,cortex-a7-gicarm,cortex-a15-gic  @ `   display-frontend@1e00000%2allwinner,sun6i-a31-display-frontend ]u5|u ahbmodram! ports port@1 endpoint@0%/endpoint@1&)display-frontend@1e20000%2allwinner,sun6i-a31-display-frontend ^u6}v ahbmodram" ports port@1 endpoint@0'0endpoint@1(*display-backend@1e40000$2allwinner,sun6i-a31-display-backend `u4{x ahbmodram {ports port@0 endpoint@0)&endpoint@1*(port@1 endpoint@1+,drc@1e500002allwinner,sun6i-a31-drc [u<r ahbmodram(ports port@0 endpoint@1,+port@1 endpoint@0-endpoint@1.display-backend@1e60000$2allwinner,sun6i-a31-display-backend _u3zw ahbmodramzports port@0 endpoint@0/%endpoint@10'port@1 endpoint@012drc@1e700002allwinner,sun6i-a31-drc [u;q ahbmodram'ports port@0 endpoint@021port@1 endpoint@03 endpoint@14rtc@1f000002allwinner,sun6i-a31-rtcT()interrupt-controller@1f00c002allwinner,sun6i-a31-r-intc  prcm@1f014002allwinner,sun6i-a31-prcmar100_clk2allwinner,sun6i-a31-ar100-clkuu  ar1005ahb0_clk2fixed-factor-clockuu5ahb06apb0_clk2allwinner,sun6i-a31-apb0-clkuu6apb07apb0_gates_clk#2allwinner,sun6i-a31-apb0-gates-clkuu7Dapb0_pioapb0_irapb0_timerapb0_p2wiapb0_uartapb0_1wireapb0_i2c8ir_clku2allwinner,sun4i-a10-mod0-clkuir9apb0_rst 2allwinner,sun6i-a31-clock-reset:cpucfg@1f01c002allwinner,sun6i-a31-cpuconfigir@1f020002allwinner,sun5i-a13-ir u89apbir: % @ |disabledpinctrl@1f02c002allwinner,sun6i-a31-r-pinctrl,-.u8apbhosclosc: s-ir-rx-pinPL4s_irs-p2wi-pinsPL0PL1s_p2wi;i2c@1f034002allwinner,sun6i-a31-p2wi4 'u8:default; |disabled ahci-5v2regulator-fixedahci-5vLK@LK@  |disabledusb0-vbus2regulator-fixed usb0-vbusLK@LK@   |disabledusb1-vbus2regulator-fixed usb1-vbusLK@LK@  |disabledusb2-vbus2regulator-fixed usb2-vbusLK@LK@ |okayvcc3v02regulator-fixedvcc3v0--vcc3v32regulator-fixedvcc3v32Z2Zvcc5v02regulator-fixedvcc5v0LK@LK@i2c 2i2c-gpiodefault< +$ interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0serial0rangesstdout-pathallwinner,pipelineclocksstatusinterruptsclock-frequencyarm,cpu-registers-not-fw-configuredenable-methoddevice_typeregclock-latencyoperating-points#cooling-cellsphandlepolling-delay-passivepolling-delaythermal-sensorstripcooling-devicetemperaturehysteresis#clock-cellsclock-output-namesallwinner,pipelinesresets#dma-cellsreset-namesclock-namesremote-endpointallwinner,tcon-channelpinctrl-namespinctrl-0vmmc-supplybus-widthcd-gpiosdma-namesdmasinterrupt-namesphysphy-namesextconreg-names#phy-cellsusb2_vbus-supply#reset-cellsgpio-controllerinterrupt-controller#interrupt-cells#gpio-cellspinsfunctiondrive-strengthbias-pull-up#sound-dai-cells#thermal-sensor-cellsreg-shiftreg-io-widthsnps,pblsnps,fixed-burstsnps,force_sf_dma_modephyphy-modeassigned-clocksassigned-clock-ratesclock-divclock-multregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onenable-active-highgpioi2c-gpio,delay-us