Ð þíÊ\8Âh(ôÂ0nvidia,beavernvidia,tegra30&'7NVIDIA Tegra30 Beaver evaluation boardchosen=serial0:115200n8aliasesI/i2c@7000d000/tps65911@2dN/rtc@7000e000S/serial@70006000memory[memoryg€ðpcie-controller@00003000nvidia,tegra30-pcie[pcig08 kpadsaficsubc €intrmsi¡ ´bÂÿÌ‚‚‚@@‚ Â(( ÓFHÁ×Úpexafipll_ecmlæFHJípexafipcie_xùokay"6G\pci@1,0[pcil‚gùokayÌpci@2,0[pcil‚g ùdisabledÌpci@3,0[pcil‚@gùokayÌhost1x@50000000!nvidia,tegra30-host1xsimple-busgP@uACÓæíhost1x ÌTTmpe@54040000nvidia,tegra30-mpegT uDÓ<æ<ímpevi@54080000nvidia,tegra30-vigT uEÓ¤æíviepp@540c0000nvidia,tegra30-eppgT  uFÓæíeppisp@54100000nvidia,tegra30-ispgT uGÓæíispgr2d@54140000nvidia,tegra30-gr2dgT uHÓæí2dgr3d@54180000nvidia,tegra30-gr3dgTÓbÚ3d3d2æbí3d3d2dc@54200000$nvidia,tegra30-dcnvidia,tegra20-dcgT  uIÓ³ Údcparentæídc—rgb ùdisableddc@54240000nvidia,tegra30-dcgT$ uJÓ³ Údcparentæídc—rgb ùdisabledhdmi@54280000nvidia,tegra30-hdmigT( uKÓ3½ Úhdmiparentæ3íhdmiùokay£¯+  º oÊ tvo@542c0000nvidia,tegra30-tvogT, uLÓ© ùdisableddsi@54300000nvidia,tegra30-dsigT0Ó0æ0ídsi ùdisabledtimer@50040600arm,cortex-a9-twd-timergP & u ÓÖinterrupt-controller@50041000arm,cortex-a9-gicgPPÝ&òøcache-controller@50043000arm,pl310-cachegP0  !/interrupt-controller@60004000nvidia,tegra30-ictlr(g`@`AP`BP`CP`DPÝ&òøtimer@60005000*nvidia,tegra30-timernvidia,tegra20-timerg`PHu)*yzÓclock@60006000nvidia,tegra30-carg``;Hòøflow-controller@60007000nvidia,tegra30-flowctrlg`pdma@6000a000,nvidia,tegra30-apbdmanvidia,tegra20-apbdmag` €uhijklmnopqrstuvw€‚ƒ„…†‡ˆ‰Š‹ŒŽÓ"æ"ídmaUò ø ahb@6000c000nvidia,tegra30-ahbg`ÀPgpio@6000d000nvidia,tegra30-gpiog`Ð`u !"#7WY}`lÝò ø apbmisc@70000800.nvidia,tegra30-apbmiscnvidia,tegra20-apbmiscgpdppinmux@70000868nvidia,tegra30-pinmuxgphÔp0ä|defaultŠ pinmuxò ø clk_32k_out_pa0”clk_32k_out_pa0 blink°¼Ìuart3_cts_n_pa1”uart3_cts_n_pa1 uartc°¼Ìdap2_fs_pa2 ”dap2_fs_pa2 i2s1°¼Ìdap2_sclk_pa3”dap2_sclk_pa3 i2s1°¼Ìdap2_din_pa4 ”dap2_din_pa4 i2s1°¼Ìdap2_dout_pa5”dap2_dout_pa5 i2s1°¼Ìsdmmc3_clk_pa6”sdmmc3_clk_pa6 sdmmc3°¼Ìsdmmc3_cmd_pa7”sdmmc3_cmd_pa7 sdmmc3°¼Ìgmi_a17_pb0 ”gmi_a17_pb0 spi4°¼Ìgmi_a18_pb1 ”gmi_a18_pb1 spi4°¼Ìlcd_pwr0_pb2 ”lcd_pwr0_pb2  displaya°¼Ìlcd_pclk_pb3 ”lcd_pclk_pb3  displaya°¼Ìsdmmc3_dat3_pb4”sdmmc3_dat3_pb4 sdmmc3°¼Ìsdmmc3_dat2_pb5”sdmmc3_dat2_pb5 sdmmc3°¼Ìsdmmc3_dat1_pb6”sdmmc3_dat1_pb6 sdmmc3°¼Ìsdmmc3_dat0_pb7”sdmmc3_dat0_pb7 sdmmc3°¼Ìuart3_rts_n_pc0”uart3_rts_n_pc0 uartc°¼Ìlcd_pwr1_pc1 ”lcd_pwr1_pc1  displaya°¼Ìuart2_txd_pc2”uart2_txd_pc2 uartb°¼Ìuart2_rxd_pc3”uart2_rxd_pc3 uartb°¼Ìgen1_i2c_scl_pc4”gen1_i2c_scl_pc4 i2c1°¼Ìàgen1_i2c_sda_pc5”gen1_i2c_sda_pc5 i2c1°¼Ìàlcd_pwr2_pc6 ”lcd_pwr2_pc6  displaya°¼Ìgmi_wp_n_pc7 ”gmi_wp_n_pc7 gmi°¼Ìsdmmc3_dat5_pd0”sdmmc3_dat5_pd0 sdmmc3°¼Ìsdmmc3_dat4_pd1”sdmmc3_dat4_pd1 sdmmc3°¼Ìlcd_dc1_pd2 ”lcd_dc1_pd2  displaya°¼Ìsdmmc3_dat6_pd3”sdmmc3_dat6_pd3 rsvd1°¼Ìsdmmc3_dat7_pd4”sdmmc3_dat7_pd4 rsvd1°¼Ìvi_d1_pd5 ”vi_d1_pd5 sdmmc2°¼Ìvi_vsync_pd6 ”vi_vsync_pd6 rsvd1°¼Ìvi_hsync_pd7 ”vi_hsync_pd7 rsvd1°¼Ìlcd_d0_pe0 ”lcd_d0_pe0  displaya°¼Ìlcd_d1_pe1 ”lcd_d1_pe1  displaya°¼Ìlcd_d2_pe2 ”lcd_d2_pe2  displaya°¼Ìlcd_d3_pe3 ”lcd_d3_pe3  displaya°¼Ìlcd_d4_pe4 ”lcd_d4_pe4  displaya°¼Ìlcd_d5_pe5 ”lcd_d5_pe5  displaya°¼Ìlcd_d6_pe6 ”lcd_d6_pe6  displaya°¼Ìlcd_d7_pe7 ”lcd_d7_pe7  displaya°¼Ìlcd_d8_pf0 ”lcd_d8_pf0  displaya°¼Ìlcd_d9_pf1 ”lcd_d9_pf1  displaya°¼Ìlcd_d10_pf2 ”lcd_d10_pf2  displaya°¼Ìlcd_d11_pf3 ”lcd_d11_pf3  displaya°¼Ìlcd_d12_pf4 ”lcd_d12_pf4  displaya°¼Ìlcd_d13_pf5 ”lcd_d13_pf5  displaya°¼Ìlcd_d14_pf6 ”lcd_d14_pf6  displaya°¼Ìlcd_d15_pf7 ”lcd_d15_pf7  displaya°¼Ìgmi_ad0_pg0 ”gmi_ad0_pg0 nand°¼Ìgmi_ad1_pg1 ”gmi_ad1_pg1 nand°¼Ìgmi_ad2_pg2 ”gmi_ad2_pg2 nand°¼Ìgmi_ad3_pg3 ”gmi_ad3_pg3 nand°¼Ìgmi_ad4_pg4 ”gmi_ad4_pg4 nand°¼Ìgmi_ad5_pg5 ”gmi_ad5_pg5 nand°¼Ìgmi_ad6_pg6 ”gmi_ad6_pg6 nand°¼Ìgmi_ad7_pg7 ”gmi_ad7_pg7 nand°¼Ìgmi_ad8_ph0 ”gmi_ad8_ph0 pwm0°¼Ìgmi_ad9_ph1 ”gmi_ad9_ph1 pwm1°¼Ìgmi_ad10_ph2 ”gmi_ad10_ph2 nand°¼Ìgmi_ad11_ph3 ”gmi_ad11_ph3 nand°¼Ìgmi_ad12_ph4 ”gmi_ad12_ph4 nand°¼Ìgmi_ad13_ph5 ”gmi_ad13_ph5 nand°¼Ìgmi_ad14_ph6 ”gmi_ad14_ph6 nand°¼Ìgmi_wr_n_pi0 ”gmi_wr_n_pi0 nand°¼Ìgmi_oe_n_pi1 ”gmi_oe_n_pi1 nand°¼Ìgmi_dqs_pi2 ”gmi_dqs_pi2 nand°¼Ìgmi_iordy_pi5”gmi_iordy_pi5 rsvd1°¼Ìgmi_cs7_n_pi6”gmi_cs7_n_pi6 nand°¼Ìgmi_wait_pi7 ”gmi_wait_pi7 nand°¼Ìlcd_de_pj1 ”lcd_de_pj1  displaya°¼Ìlcd_hsync_pj3”lcd_hsync_pj3  displaya°¼Ìlcd_vsync_pj4”lcd_vsync_pj4  displaya°¼Ìuart2_cts_n_pj5”uart2_cts_n_pj5 uartb°¼Ìuart2_rts_n_pj6”uart2_rts_n_pj6 uartb°¼Ìgmi_a16_pj7 ”gmi_a16_pj7 spi4°¼Ìgmi_adv_n_pk0”gmi_adv_n_pk0 nand°¼Ìgmi_clk_pk1 ”gmi_clk_pk1 nand°¼Ìgmi_cs2_n_pk3”gmi_cs2_n_pk3 rsvd1°¼Ìgmi_cs3_n_pk4”gmi_cs3_n_pk4 nand°¼Ìspdif_out_pk5”spdif_out_pk5 spdif°¼Ìspdif_in_pk6 ”spdif_in_pk6 spdif°¼Ìgmi_a19_pk7 ”gmi_a19_pk7 spi4°¼Ìvi_d2_pl0 ”vi_d2_pl0 sdmmc2°¼Ìvi_d3_pl1 ”vi_d3_pl1 sdmmc2°¼Ìvi_d4_pl2 ”vi_d4_pl2 vi°¼Ìvi_d5_pl3 ”vi_d5_pl3 sdmmc2°¼Ìvi_d6_pl4 ”vi_d6_pl4 vi°¼Ìvi_d7_pl5 ”vi_d7_pl5 sdmmc2°¼Ìvi_d8_pl6 ”vi_d8_pl6 sdmmc2°¼Ìvi_d9_pl7 ”vi_d9_pl7 sdmmc2°¼Ìlcd_d16_pm0 ”lcd_d16_pm0  displaya°¼Ìlcd_d17_pm1 ”lcd_d17_pm1  displaya°¼Ìlcd_d18_pm2 ”lcd_d18_pm2  displaya°¼Ìlcd_d19_pm3 ”lcd_d19_pm3  displaya°¼Ìlcd_d20_pm4 ”lcd_d20_pm4  displaya°¼Ìlcd_d21_pm5 ”lcd_d21_pm5  displaya°¼Ìlcd_d22_pm6 ”lcd_d22_pm6  displaya°¼Ìlcd_d23_pm7 ”lcd_d23_pm7  displaya°¼Ìdap1_fs_pn0 ”dap1_fs_pn0 i2s0°¼Ìdap1_din_pn1 ”dap1_din_pn1 i2s0°¼Ìdap1_dout_pn2”dap1_dout_pn2 i2s0°¼Ìdap1_sclk_pn3”dap1_sclk_pn3 i2s0°¼Ìlcd_cs0_n_pn4”lcd_cs0_n_pn4  displaya°¼Ìlcd_sdout_pn5”lcd_sdout_pn5  displaya°¼Ìlcd_dc0_pn6 ”lcd_dc0_pn6  displaya°¼Ìhdmi_int_pn7 ”hdmi_int_pn7 rsvd1°¼Ìulpi_data7_po0”ulpi_data7_po0 uarta°¼Ìulpi_data0_po1”ulpi_data0_po1 uarta°¼Ìulpi_data1_po2”ulpi_data1_po2 uarta°¼Ìulpi_data2_po3”ulpi_data2_po3 uarta°¼Ìulpi_data3_po4”ulpi_data3_po4 rsvd1°¼Ìulpi_data4_po5”ulpi_data4_po5 uarta°¼Ìulpi_data5_po6”ulpi_data5_po6 uarta°¼Ìulpi_data6_po7”ulpi_data6_po7 uarta°¼Ìdap3_fs_pp0 ”dap3_fs_pp0 i2s2°¼Ìdap3_din_pp1 ”dap3_din_pp1 i2s2°¼Ìdap3_dout_pp2”dap3_dout_pp2 i2s2°¼Ìdap3_sclk_pp3”dap3_sclk_pp3 i2s2°¼Ìdap4_fs_pp4 ”dap4_fs_pp4 i2s3°¼Ìdap4_din_pp5 ”dap4_din_pp5 i2s3°¼Ìdap4_dout_pp6”dap4_dout_pp6 i2s3°¼Ìdap4_sclk_pp7”dap4_sclk_pp7 i2s3°¼Ìkb_col0_pq0 ”kb_col0_pq0 kbc°¼Ìkb_col1_pq1 ”kb_col1_pq1 kbc°¼Ìkb_col2_pq2 ”kb_col2_pq2 kbc°¼Ìkb_col3_pq3 ”kb_col3_pq3 kbc°¼Ìkb_col4_pq4 ”kb_col4_pq4 kbc°¼Ìkb_col5_pq5 ”kb_col5_pq5 kbc°¼Ìkb_col6_pq6 ”kb_col6_pq6 kbc°¼Ìkb_col7_pq7 ”kb_col7_pq7 kbc°¼Ìkb_row0_pr0 ”kb_row0_pr0 kbc°¼Ìkb_row1_pr1 ”kb_row1_pr1 kbc°¼Ìkb_row2_pr2 ”kb_row2_pr2 kbc°¼Ìkb_row3_pr3 ”kb_row3_pr3 kbc°¼Ìkb_row4_pr4 ”kb_row4_pr4 kbc°¼Ìkb_row5_pr5 ”kb_row5_pr5 kbc°¼Ìkb_row6_pr6 ”kb_row6_pr6 kbc°¼Ìkb_row7_pr7 ”kb_row7_pr7 kbc°¼Ìkb_row8_ps0 ”kb_row8_ps0 kbc°¼Ìkb_row9_ps1 ”kb_row9_ps1 kbc°¼Ìkb_row10_ps2 ”kb_row10_ps2 kbc°¼Ìkb_row11_ps3 ”kb_row11_ps3 kbc°¼Ìkb_row12_ps4 ”kb_row12_ps4 kbc°¼Ìkb_row13_ps5 ”kb_row13_ps5 kbc°¼Ìkb_row14_ps6 ”kb_row14_ps6 kbc°¼Ìkb_row15_ps7 ”kb_row15_ps7 kbc°¼Ìvi_pclk_pt0 ”vi_pclk_pt0 rsvd1°¼Ìvi_mclk_pt1 ”vi_mclk_pt1 vi°¼Ìvi_d10_pt2 ”vi_d10_pt2 rsvd1°¼Ìvi_d11_pt3 ”vi_d11_pt3 rsvd1°¼Ìvi_d0_pt4 ”vi_d0_pt4 rsvd1°¼Ìgen2_i2c_scl_pt5”gen2_i2c_scl_pt5 i2c2°¼Ìàgen2_i2c_sda_pt6”gen2_i2c_sda_pt6 i2c2°¼Ìàsdmmc4_cmd_pt7”sdmmc4_cmd_pt7 sdmmc4°¼Ìpu0”pu0 rsvd1°¼Ìpu1”pu1 rsvd1°¼Ìpu2”pu2 rsvd1°¼Ìpu3”pu3 rsvd1°¼Ìpu4”pu4 pwm1°¼Ìpu5”pu5 pwm2°¼Ìpu6”pu6 rsvd1°¼Ìjtag_rtck_pu7”jtag_rtck_pu7 rtck°¼Ìpv0”pv0 rsvd1°¼Ìpv2”pv2 owr°¼Ìpv3”pv3 rsvd1°¼Ìddc_scl_pv4 ”ddc_scl_pv4 i2c4°¼Ìddc_sda_pv5 ”ddc_sda_pv5 i2c4°¼Ìcrt_hsync_pv6”crt_hsync_pv6 crt°¼Ìcrt_vsync_pv7”crt_vsync_pv7 crt°¼Ìlcd_cs1_n_pw0”lcd_cs1_n_pw0  displaya°¼Ìlcd_m1_pw1 ”lcd_m1_pw1  displaya°¼Ìspi2_cs1_n_pw2”spi2_cs1_n_pw2 spi2°¼Ìclk1_out_pw4 ”clk1_out_pw4  extperiph1°¼Ìclk2_out_pw5 ”clk2_out_pw5  extperiph2°¼Ìuart3_txd_pw6”uart3_txd_pw6 uartc°¼Ìuart3_rxd_pw7”uart3_rxd_pw7 uartc°¼Ìspi2_sck_px2 ”spi2_sck_px2 gmi°¼Ìspi1_mosi_px4”spi1_mosi_px4 spi1°¼Ìspi1_sck_px5 ”spi1_sck_px5 spi1°¼Ìspi1_cs0_n_px6”spi1_cs0_n_px6 spi1°¼Ìspi1_miso_px7”spi1_miso_px7 spi1°¼Ìulpi_clk_py0 ”ulpi_clk_py0 uartd°¼Ìulpi_dir_py1 ”ulpi_dir_py1 uartd°¼Ìulpi_nxt_py2 ”ulpi_nxt_py2 uartd°¼Ìulpi_stp_py3 ”ulpi_stp_py3 uartd°¼Ìsdmmc1_dat3_py4”sdmmc1_dat3_py4 sdmmc1°¼Ìsdmmc1_dat2_py5”sdmmc1_dat2_py5 sdmmc1°¼Ìsdmmc1_dat1_py6”sdmmc1_dat1_py6 sdmmc1°¼Ìsdmmc1_dat0_py7”sdmmc1_dat0_py7 sdmmc1°¼Ìsdmmc1_clk_pz0”sdmmc1_clk_pz0 sdmmc1°¼Ìsdmmc1_cmd_pz1”sdmmc1_cmd_pz1 sdmmc1°¼Ìlcd_sdin_pz2 ”lcd_sdin_pz2  displaya°¼Ìlcd_wr_n_pz3 ”lcd_wr_n_pz3  displaya°¼Ìlcd_sck_pz4 ”lcd_sck_pz4  displaya°¼Ìsys_clk_req_pz5”sys_clk_req_pz5 sysclk°¼Ìpwr_i2c_scl_pz6”pwr_i2c_scl_pz6 i2cpwr°¼Ìàpwr_i2c_sda_pz7”pwr_i2c_sda_pz7 i2cpwr°¼Ìàsdmmc4_dat0_paa0”sdmmc4_dat0_paa0 sdmmc4°¼Ìsdmmc4_dat1_paa1”sdmmc4_dat1_paa1 sdmmc4°¼Ìsdmmc4_dat2_paa2”sdmmc4_dat2_paa2 sdmmc4°¼Ìsdmmc4_dat3_paa3”sdmmc4_dat3_paa3 sdmmc4°¼Ìsdmmc4_dat4_paa4”sdmmc4_dat4_paa4 sdmmc4°¼Ìsdmmc4_dat5_paa5”sdmmc4_dat5_paa5 sdmmc4°¼Ìsdmmc4_dat6_paa6”sdmmc4_dat6_paa6 sdmmc4°¼Ìsdmmc4_dat7_paa7”sdmmc4_dat7_paa7 sdmmc4°¼Ìpbb0”pbb0 rsvd1°¼Ìcam_i2c_scl_pbb1”cam_i2c_scl_pbb1 i2c3°¼Ìàcam_i2c_sda_pbb2”cam_i2c_sda_pbb2 i2c3°¼Ìàpbb3”pbb3 vgp3°¼Ìpbb4”pbb4 vgp4°¼Ìpbb5”pbb5 vgp5°¼Ìpbb6”pbb6 vgp6°¼Ìpbb7”pbb7 i2s4°¼Ìcam_mclk_pcc0”cam_mclk_pcc0 vi_alt3°¼Ìpcc1”pcc1 rsvd1°¼Ìpcc2”pcc2 i2s4°¼Ìsdmmc4_rst_n_pcc3”sdmmc4_rst_n_pcc3 sdmmc4°¼Ìsdmmc4_clk_pcc4”sdmmc4_clk_pcc4 sdmmc4°¼Ìclk2_req_pcc5”clk2_req_pcc5 dap°¼Ìpex_l2_rst_n_pcc6”pex_l2_rst_n_pcc6 pcie°¼Ìpex_l2_clkreq_n_pcc7”pex_l2_clkreq_n_pcc7 pcie°¼Ìpex_l0_prsnt_n_pdd0”pex_l0_prsnt_n_pdd0 pcie°¼Ìpex_l0_rst_n_pdd1”pex_l0_rst_n_pdd1 pcie°¼Ìpex_l0_clkreq_n_pdd2”pex_l0_clkreq_n_pdd2 pcie°¼Ìpex_wake_n_pdd3”pex_wake_n_pdd3 pcie°¼Ìpex_l1_prsnt_n_pdd4”pex_l1_prsnt_n_pdd4 pcie°¼Ìpex_l1_rst_n_pdd5”pex_l1_rst_n_pdd5 pcie°¼Ìpex_l1_clkreq_n_pdd6”pex_l1_clkreq_n_pdd6 pcie°¼Ìpex_l2_prsnt_n_pdd7”pex_l2_prsnt_n_pdd7 pcie°¼Ìclk3_out_pee0”clk3_out_pee0  extperiph3°¼Ìclk3_req_pee1”clk3_req_pee1 dev3°¼Ìclk1_req_pee2”clk1_req_pee2 dap°¼Ìhdmi_cec_pee3”hdmi_cec_pee3 cec°¼Ìàowr”owr owr°¼Ìsdio3 ”drive_sdio3ò .2*Jbgpv ”drive_gpv2serial@70006000(nvidia,tegra30-uartnvidia,tegra20-uartgp`@{ u$Óæíserial…  Šrxtxùokayserial@70006040(nvidia,tegra30-uartnvidia,tegra20-uartgp`@@{ u%Ó æíserial… Šrxtx ùdisabledserial@70006200(nvidia,tegra30-uartnvidia,tegra20-uartgpb{ u.Ó7æ7íserial… Šrxtx ùdisabledserial@70006300(nvidia,tegra30-uartnvidia,tegra20-uartgpc{ uZÓAæAíserial…  Šrxtx ùdisabledserial@70006400(nvidia,tegra30-uartnvidia,tegra20-uartgpd{ u[ÓBæBíserial…  Šrxtx ùdisabledgmi@70009000nvidia,tegra30-gmigpÌHÿÿÿÓ*Úgmiæ*ígmi ùdisabledpwm@7000a000&nvidia,tegra30-pwmnvidia,tegra20-pwmgp ”Óæípwm ùdisabledrtc@7000e000&nvidia,tegra30-rtcnvidia,tegra20-rtcgpà uÓi2c@7000c000&nvidia,tegra30-i2cnvidia,tegra20-i2cgpÀ u&Ó ¶Údiv-clkfast-clkæ íi2c…  ŠrxtxùokayŸ† i2c@7000c400&nvidia,tegra30-i2cnvidia,tegra20-i2cgpÄ uTÓ6¶Údiv-clkfast-clkæ6íi2c…  ŠrxtxùokayŸ† i2c@7000c500&nvidia,tegra30-i2cnvidia,tegra20-i2cgpÅ u\ÓC¶Údiv-clkfast-clkæCíi2c…  ŠrxtxùokayŸ† i2c@7000c700&nvidia,tegra30-i2cnvidia,tegra20-i2cgpÇ uxÓg¶ægíi2cÚdiv-clkfast-clk…  ŠrxtxùokayŸ† ò ø i2c@7000d000&nvidia,tegra30-i2cnvidia,tegra20-i2cgpÐ u5Ó/¶Údiv-clkfast-clkæ/íi2c…  ŠrxtxùokayŸ† rt5640@1crealtek,rt5640g& u» ¯ ºòøtps65911@2d ti,tps65911g- uVÝÅ`làìø (4òøregulatorsvdd1Avddio_ddr_1v2PO€hO€€vdd2 Avdd_1v5_genPã`hã`€òøvddctrlAvdd_cpu,vdd_sysPB@hB@€vio Avdd_1v8_genPw@hw@€ò ø ldo1Avdd_pexa,vdd_pexbPhòøldo2Avdd_sata,avdd_pllePhldo4Avdd_rtcPO€hO€€ldo5Avddio_sdmmc,avdd_vdacPw@h2Z €òøldo6Aavdd_dsi_csi,pwrdet_mipiPO€hO€ldo7Avdd_pllm,x,u,a_p_c_sPO€hO€€ldo8 Avdd_ddr_hsPB@hB@€tps62361@60 ti,tps62361g`Atps62361-voutP¡ hã`”€¦ºspi@7000d400*nvidia,tegra30-slinknvidia,tegra20-slinkgpÔ u;Ó)æ)íspi…  Šrxtx ùdisabledspi@7000d600*nvidia,tegra30-slinknvidia,tegra20-slinkgpÖ uRÓ,æ,íspi…  Šrxtx ùdisabledspi@7000d800*nvidia,tegra30-slinknvidia,tegra20-slinkgpØ uSÓ.æ.íspi…  Šrxtx ùdisabledspi@7000da00*nvidia,tegra30-slinknvidia,tegra20-slinkgpÚ u]ÓDæDíspi…  ŠrxtxùokayÎ}x@spi-flash@1winbond,w25q32gÎ1-spi@7000dc00*nvidia,tegra30-slinknvidia,tegra20-slinkgpÜ u^Óhæhíspi…  Šrxtx ùdisabledspi@7000de00*nvidia,tegra30-slinknvidia,tegra20-slinkgpÞ uOÓiæjíspi…  Šrxtx ùdisabledkbc@7000e200&nvidia,tegra30-kbcnvidia,tegra20-kbcgpâ uUÓ$æ$íkbc ùdisabledpmc@7000e400nvidia,tegra30-pmcgpä ÓÚÚpclkclk32k_inùokayàø Ð%È=Wp’memory-controller@7000f000nvidia,tegra30-mcgpðÓ Úmc uM³òøfuse@7000f800nvidia,tegra30-efusegpøÓ¦Úfuseæ'ífusehda@70030000nvidia,tegra30-hdagp uQÓ}€oÚhdahda2hdmihda2codec_2xæ}€oíhdahda2hdmihda2codec_2x ùdisabledahub@70080000nvidia,tegra30-ahubgpp ugÓjkÚd_audioapbifXæjk eflmn <íd_audioapbifi2s0i2s1i2s2i2s3i2s4dam0dam1dam2spdif@…         Šrx0tx0rx1tx1rx2tx2rx3tx3Ìi2s@70080300nvidia,tegra30-i2sgpÀÓæíi2s ùdisabledi2s@70080400nvidia,tegra30-i2sgpÀÓ æ íi2sùokayòøi2s@70080500nvidia,tegra30-i2sgpÀÓæíi2s ùdisabledi2s@70080600nvidia,tegra30-i2sgpÀÓeæeíi2s ùdisabledi2s@70080700nvidia,tegra30-i2sgpÀÓfæfíi2s ùdisabledsdhci@78000000*nvidia,tegra30-sdhcinvidia,tegra20-sdhcigx uÓæísdhciùokayÔ á E ê › ó ÿsdhci@78000200*nvidia,tegra30-sdhcinvidia,tegra20-sdhcigx uÓ æ ísdhci ùdisabledsdhci@78000400*nvidia,tegra30-sdhcinvidia,tegra20-sdhcigx uÓEæEísdhci ùdisabledsdhci@78000600*nvidia,tegra30-sdhcinvidia,tegra20-sdhcigx uÓæísdhciùokayÿ usb@7d000000nvidia,tegra30-ehciusb-ehcig}@ uutmiÓæíusb : ùdisabledusb-phy@7d000000nvidia,tegra30-usb-phyg}@}@utmiÓ¾Úregpll_uutmi-padsæíusbutmi-padsE _v‹¡3³Ïã÷  !7 ùdisabledòøusb@7d004000nvidia,tegra30-ehciusb-ehcig}@@ uutmiÓ:æ:íusb:ùokayusb-phy@7d004000nvidia,tegra30-usb-phyg}@@}@utmiÓ:¾Úregpll_uutmi-padsæ:íusbutmi-padsE _v‹¡3³Ïã÷  !ùokayUòøusb@7d008000nvidia,tegra30-ehciusb-ehcig}€@ uautmiÓ;æ;íusb:ùokayusb-phy@7d008000nvidia,tegra30-usb-phyg}€@}@utmiÓ;¾Úregpll_uutmi-padsæ;íusbutmi-padsE_v‹¡3³Ïã÷  !ùokayUòøcpuscpu@0[cpuarm,cortex-a9gcpu@1[cpuarm,cortex-a9gcpu@2[cpuarm,cortex-a9gcpu@3[cpuarm,cortex-a9gpmuarm,cortex-a9-pmu0u‘’“clocks simple-busclock@0 fixed-clockg;Ÿ€òøgpio-leds gpio-ledsgpled1aLED1 ¿ Ygpled2aLED2 ¿ Xregulators simple-busregulator@0regulator-fixedg Avdd_5v_inPLK@hLK@€òøregulator@1regulator-fixedgAchargepump_5vPLK@hLK@”€g Åregulator@2regulator-fixedgAvdd_ddrPã`hã`€”g Åzregulator@3regulator-fixedg Avdd_5v_sataPLK@hLK@€”g Å zregulator@4regulator-fixedg Ausb1_vbusPLK@hLK@g Å î…zregulator@5regulator-fixedg Ausb3_vbusPLK@hLK@g Å ì…zòøregulator@6regulator-fixedgAsys_3v3,vdd_3v3_alwP2Z h2Z €”g Åzòøregulator@7regulator-fixedg Asys_3v3_pexsP2Z h2Z €”g Å _zòøregulator@8regulator-fixedg A+VDD_5V_HDMIPLK@hLK@€”zòøsound;nvidia,tegra-audio-rt5640-beavernvidia,tegra-audio-rt5640•NVIDIA Tegra Beaver@¢HeadphonesHPORHeadphonesHPOLMic JackMICBIAS1IN2PMic Jack·Í à ²Ó¸¹xÚpll_apll_a_out0mclk #address-cells#size-cellscompatibleinterrupt-parentmodelstdout-pathrtc0rtc1serial0device_typeregreg-namesinterruptsinterrupt-names#interrupt-cellsinterrupt-map-maskinterrupt-mapbus-rangerangesclocksclock-namesresetsreset-namesstatusavdd-pexa-supplyavdd-pexb-supplyavdd-pex-pll-supplyavdd-plle-supplyvddio-pex-ctl-supplyhvdd-pex-supplyassigned-addressesnvidia,num-lanesiommusnvidia,headhdmi-supplyvdd-supplynvidia,hpd-gpionvidia,ddc-i2c-businterrupt-controllerlinux,phandlearm,data-latencyarm,tag-latencycache-unifiedcache-level#clock-cells#reset-cells#dma-cells#gpio-cellsgpio-controllerpinctrl-namespinctrl-0nvidia,pinsnvidia,functionnvidia,pullnvidia,tristatenvidia,enable-inputnvidia,open-drainnvidia,high-speed-modenvidia,schmittnvidia,pull-down-strengthnvidia,pull-up-strengthnvidia,slew-rate-risingnvidia,slew-rate-fallingreg-shiftdmasdma-names#pwm-cellsclock-frequencyrealtek,ldo1-en-gpiosti,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onti,vsel0-state-highti,vsel1-state-highspi-max-frequencynvidia,invert-interruptnvidia,suspend-modenvidia,cpu-pwr-good-timenvidia,cpu-pwr-off-timenvidia,core-pwr-good-timenvidia,core-pwr-off-timenvidia,core-power-req-active-highnvidia,sys-clock-req-active-high#iommu-cellsnvidia,ahub-cif-idsvqmmc-supplycd-gpioswp-gpiospower-gpiosbus-widthnon-removablephy_typenvidia,needs-double-resetnvidia,phynvidia,hssync-start-delaynvidia,idle-wait-delaynvidia,elastic-limitnvidia,term-range-adjnvidia,xcvr-setupnvidia.xcvr-setup-use-fusesnvidia,xcvr-lsfslewnvidia,xcvr-lsrslewnvidia,xcvr-hsslewnvidia,hssquelch-levelnvidia,hsdiscon-levelnvidia,has-utmi-pad-registersvbus-supplylabelenable-active-highvin-supplygpio-open-drainnvidia,modelnvidia,audio-routingnvidia,i2s-controllernvidia,audio-codecnvidia,hp-det-gpios