8d( \,&Arrow Electronics, APQ8064 SD_600eval!arrow,sd_600evalqcom,apq8064,chosenaliases#=/soc/gsbi@16600000/serial@16640000#E/soc/gsbi@12440000/serial@12450000 M/soc/gsbi@12480000/i2c@124a0000 R/soc/gsbi@16200000/i2c@16280000 W/soc/gsbi@16300000/i2c@16380000 \/soc/gsbi@16600000/i2c@16680000 a/soc/gsbi@1a200000/spi@1a280000memoryfmemoryrreserved-memoryvsmem@80000000r }wcnss@8f000000rp}OOcpuscpu@0 !qcom,kraitqcom,kpss-acc-v1fcpurddcpu@1 !qcom,kraitqcom,kpss-acc-v1fcpurffcpu@2 !qcom,kraitqcom,kpss-acc-v1fcpur hhcpu@3 !qcom,kraitqcom,kpss-acc-v1fcpur  jjl2-cache!cacheidle-statesspc#!qcom,idle-state-spcarm,idle-state thermal-zonescpu-thermal0'5 Etripstrip0R$^mpassivetrip1R^ mcriticalcpu-thermal1'5 Eltripstrip0R$^mpassivetrip1R^ mcriticalcpu-thermal2'5 Etripstrip0R$^mpassivetrip1R^ mcriticalcpu-thermal3'5 Eltripstrip0R$^mpassivetrip1R^ mcriticalcpu-pmu!qcom,krait-pmu i clockscxo_board !fixed-clockt$TTpxo_board !fixed-clocktsleep_clk !fixed-clockthwmutex!qcom,sfpb-mutex  smem !qcom,smemsmd !qcom,smdmodem@0 i%  disabledq6@1 iZ  disableddsps@3 i @ disabledriva@6 i  disabledsmsm !qcom,smsm    @apps@0rYYmodem@1r i&2q6@2r iY2wcnss@3r i2NNdsps@4r i2firmwarescm!qcom,scm-apq8064C Jcoresocv !simple-buspinctrl@800000!qcom,apq8064-pinctrlr@Vf2 irdefaultsdc4-gpios??pios*gpio63gpio64gpio65gpio66gpio67gpio68sdc4sdcc1-pin-active88clk sdc1_clkcmd sdc1_cmd data sdc1_data sdcc3-pin-activeclk sdc3_clkcmd sdc3_cmddata sdc3_dataps_holdmuxgpio78ps_holdi2c1muxgpio20gpio21gsbi1pinconfgpio20gpio21i2c1_pins_sleepmuxgpio20gpio21gpiopinconfgpio20gpio21gsbi1_uart_2pinsmuxgpio18gpio19gsbi1gsbi1_uart_4pinsmuxgpio18gpio19gpio20gpio21gsbi1i2c2muxgpio24gpio25gsbi2pinconfgpio24gpio25i2c2_pins_sleepmuxgpio24gpio25gpiopinconfgpio24gpio25i2c3mux gpio8gpio9gsbi3pinconf gpio8gpio9i2c3_pins_sleepmux gpio8gpio9gpiopinconf gpio8gpio9i2c4  muxgpio12gpio13gsbi4pinconfgpio12gpio13i2c4_pins_sleep!!muxgpio12gpio13gpiopinconfgpio12gpio13spi5_default""pinmuxgpio51gpio52gpio54gsbi5pinmux_csgpiogpio53pinconfgpio51gpio52gpio54pinconf_csgpio53spi5_sleep##pinmuxgpiogpio51gpio52gpio53gpio54pinconfgpio51gpio52gpio53gpio54i2c6$$muxgpio16gpio17gsbi6pinconfgpio16gpio17i2c6_pins_sleep%%muxgpio16gpio17gpiopinconfgpio16gpio17gsbi6_uart_2pinsmuxgpio14gpio15gsbi6gsbi6_uart_4pinsmuxgpio14gpio15gpio16gpio17gsbi6gsbi7_uart_2pins&&muxgpio82gpio83gsbi7gsbi7_uart_4pinsmuxgpio82gpio83gpio84gpio85gsbi7i2c7''muxgpio84gpio85gsbi7pinconfgpio84gpio85i2c7_pins_sleep((muxgpio84gpio85gpiopinconfgpio84gpio85riva-fm-activegpio14gpio15riva_fmSSriva-bt-activegpio16gpio17riva_btRRriva-wlan-active#gpio64gpio65gpio66gpio67gpio68 riva_wlanQQhdmi-pinctrlGGmuxgpio70gpio71gpio72hdmipinconf_ddcgpio70gpio71pinconf_hpdgpio72card-detect==muxgpio26gpiopcie-pinmuxFFmuxgpio27gpioconfgpio27 user-ledsllmuxgpio3gpio7gpio10gpio11gpioconfgpio3gpio7gpio10gpio11gpiomagneto-pinsmuxgpio31gpio48gpiosyscon@1200000!sysconr   interrupt-controller@2000000!qcom,msm-qgic22r timer@200a0005!qcom,kpss-timerqcom,kpss-wdt-apq8064qcom,msm-timer$irclock-controller@2088000!qcom,kpss-acc-v1rclock-controller@2098000!qcom,kpss-acc-v1r clock-controller@20a8000!qcom,kpss-acc-v1r clock-controller@20b8000!qcom,kpss-acc-v1r   power-controller@2089000%!qcom,apq8064-saw2-v1.1-cpuqcom,saw2rpower-controller@2099000%!qcom,apq8064-saw2-v1.1-cpuqcom,saw2r power-controller@20a9000%!qcom,apq8064-saw2-v1.1-cpuqcom,saw2r   power-controller@20b9000%!qcom,apq8064-saw2-v1.1-cpuqcom,saw2r   sps-sic-non-secure@12100000!sysconrgsbi@12440000okay!qcom,gsbi-v1.0.0 rDC Jifacev!serial@12450000%!qcom,msm-uartdm-v1.3qcom,msm-uartdmrE@ iC  Jcoreifaceokay +LS-UART1rdefaulti2c@12460000!qcom,i2c-qup-v1.1.11rdefaultsleeprF iC  Jcoreifacegsbi@12480000okay!qcom,gsbi-v1.0.0 rHC Jifacev!i2c@124a0000!qcom,i2c-qup-v1.1.1rJ1rdefaultsleep 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qJmclkapb_pclkl>>txrxrdefault?syscon@1a400000!qcom,tcsr-apq8064sysconr@adreno-3xx@4300000!qcom,adreno-3xxr0:kgsl_3d0_reg_memory iP kgsl_3d0_irq)Jcore_clkiface_clkmem_clkmem_iface_clk C@G@@!@P\AAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAABBBBBBBBBB B B B B BBBBBBBBBBBBBBBBBBqcom,gpu-pwrlevels!qcom,gpu-pwrlevelsqcom,gpu-pwrlevel@0ctqcom,gpu-pwrlevel@1csyscon@5700000!sysconrppDDmdss_dsi@4700000!qcom,mdss-dsi-ctrl+MDSS DSI CTRL->0 iRrp :dsi_ctrl8C@@@@9@T@j@XDJiface_clkbus_clkcore_mmss_clksrc_clkbyte_clkpixel_clkcore_clk O@S@W@8@i qCCCCDtCportsport@0rendpointport@1rendpointdsi-phy@4700200!qcom,dsi-phy-28nm-8960trppp\":dsi_plldsi_phydsi_phy_regulator Jiface_clkC@CCiommu@7500000!qcom,apq8064-iommuJsmmu_pclkiommu_clkC@ @rPi?@KKiommu@7600000!qcom,apq8064-iommuJsmmu_pclkiommu_clkC@ @r`i=>LLiommu@7c00000!qcom,apq8064-iommuJsmmu_pclkiommu_clkC@ @!riEFAAiommu@7d00000!qcom,apq8064-iommuJsmmu_pclkiommu_clkC@ @!riBBpci@1b500000!qcom,pcie-apq8064snps,dw-pcie rPP `:dbielbiparfconfigfpci0v imsi2$%&'C + . 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#address-cells#size-cellsmodelcompatibleinterrupt-parentserial0serial1i2c0i2c1i2c2i2c3spi0device_typeregrangesno-maplinux,phandleenable-methodnext-level-cacheqcom,accqcom,sawcpu-idle-statescache-levelentry-latency-usexit-latency-usmin-residency-uspolling-delay-passivepolling-delaythermal-sensorscoefficientstemperaturehysteresisinterrupts#clock-cellsclock-frequencysyscon#hwlock-cellsmemory-regionhwlocksqcom,ipcqcom,smd-edgestatusqcom,ipc-1qcom,ipc-2qcom,ipc-3qcom,ipc-4#qcom,smem-state-cellsinterrupt-controller#interrupt-cellsclocksclock-namesgpio-controller#gpio-cellspinctrl-namespinctrl-0pinsfunctiondrive-strenghbias-disablebias-pull-updrive-strengthoutput-highbias-pull-downoutput-lowcpu-offsetregulatorcell-indexsyscon-tcsrqcom,modelabelpinctrl-1vdd-supplyvddio-supplyst,drdy-int-pinpagesizeqcom,controller-typeallow-set-timedebouncenvmem-cellsnvmem-cell-names#reset-cells#thermal-sensor-cellsinterrupt-namesvdd_s1-supplyvdd_s2-supplyvdd_s3-supplyvdd_s4-supplyvdd_s5-supplyvdd_s6-supplyvdd_s7-supplyvdd_l1_l2_l12_l18-supplyvdd_l3_l15_l17-supplyvdd_l4_l14-supplyvdd_l5_l8_l16-supplyvdd_l6_l7-supplyvdd_l9_l11-supplyvdd_l10_l22-supplyvdd_l21_l23_l29-supplyvdd_l24-supplyvdd_l25-supplyvdd_l26-supplyvdd_l27-supplyvdd_l28-supplyvin_lvs1_3_6-supplyvin_lvs2-supplyvin_lvs4_5_7-supplyregulator-always-onregulator-min-microvoltregulator-max-microvoltqcom,switch-mode-frequencyqcom,force-moderegulator-boot-onresetsreset-namesdr_modevddcx-supplyv3p3-supplyv1p8-supplyusb-phyreg-names#phy-cellsassigned-clocksassigned-clock-ratesphysphy-namesports-implementedtarget-supply#dma-cellsqcom,eearm,primecell-periphidbus-widthmax-frequencynon-removablecap-sd-highspeedcap-mmc-highspeeddmasdma-namesvmmc-supplyvqmmc-supplyno-1-8-vcd-gpiosqcom,chipidiommusqcom,gpu-freqassigned-clock-parentssyscon-sfpb#iommu-cellsqcom,ncblinux,pci-domainbus-rangenum-lanesinterrupt-map-maskinterrupt-mapvdda-supplyvdda_phy-supplyvdda_refclk-supplyperst-gpiocore-vdda-supplyhdmi-mux-supplyhpd-gpioremote-endpointinterrupts-extendedvddmx-supplyvddpx-supplyvddxo-supplyvddrfa-supplyvddpa-supplyvdddig-supplyqcom,smd-channelsqcom,mmioqcom,smem-statesqcom,smem-state-namesslave-modecpulinux,default-triggerdefault-stateregulator-nameregulator-type