8(LGtechnexion,omap3-thundertechnexion,omap3-tao3530ti,omap34xxti,omap3 +,7TI OMAP3 Thunder baseboard with TAO3530 SOMchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+ *pinmux_hsusbb2_pins`G          pinmux_mmc1_pinsPG "$&[apinmux_mmc2_pins0G(*,.02[apinmux_wlan_gpioG^pinmux_uart3_pinsGnAp[apinmux_i2c3_pinsG[apinmux_mcspi1_pins G[apinmux_mcspi3_pins G[apinmux_mcbsp3_pins G<>@B[apinmux_twl4030_pinsGA[apinmux_dss_dpi_pinsG[apinmux_lte430_pinsG8[apinmux_backlight_pinsG:[ascm_conf@270sysconsimple-busyp0+ p0[apbias_regulator@2b0ti,pbias-omap3ti,pbias-omapyipbias_mmc_omap2430ppbias_mmc_omap2430w@-[aclocks+mcbsp5_mux_fck@68ti,composite-mux-clock}yh[amcbsp5_fckti,composite-clock}[amcbsp1_mux_fck@4ti,composite-mux-clock}y[ a mcbsp1_fckti,composite-clock} [amcbsp2_mux_fck@4ti,composite-mux-clock} y[ a mcbsp2_fckti,composite-clock} [amcbsp3_mux_fck@68ti,composite-mux-clock} yh[amcbsp3_fckti,composite-clock}[amcbsp4_mux_fck@68ti,composite-mux-clock} yh[amcbsp4_fckti,composite-clock}[aclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+ *pinmux_twl4030_vpins G[aaes@480c5000 ti,omap3-aesaesyH PPABtxrx disabledprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockY[aosc_sys_ck@d40 ti,mux-clock}y @[asys_ck@1270ti,divider-clock}yp[asys_clkout1@d70ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock}dpll3_m2x2_ckfixed-factor-clock}[adpll4_x2_ckfixed-factor-clock}corex2_fckfixed-factor-clock}[awkup_l4_ickfixed-factor-clock}[NaNcorex2_d3_fckfixed-factor-clock}[acorex2_d5_fckfixed-factor-clock}[aclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock[@a@virt_12m_ck fixed-clock[avirt_13m_ck fixed-clock]@[avirt_19200000_ck fixed-clock$[avirt_26000000_ck fixed-clock[avirt_38_4m_ck fixed-clockI[adpll4_ck@d00ti,omap3-dpll-per-clock}y D 0[adpll4_m2_ck@d48ti,divider-clock}?y H[ a dpll4_m2x2_mul_ckfixed-factor-clock} [!a!dpll4_m2x2_ck@d00ti,gate-clock}!y &["a"omap_96m_alwon_fckfixed-factor-clock}"[)a)dpll3_ck@d00ti,omap3-dpll-core-clock}y @ 0[adpll3_m3_ck@1140ti,divider-clock}y@[#a#dpll3_m3x2_mul_ckfixed-factor-clock}#[$a$dpll3_m3x2_ck@d00ti,gate-clock}$ y &[%a%emu_core_alwon_ckfixed-factor-clock}%[babsys_altclk fixed-clock[.a.mcbsp_clks fixed-clock[adpll3_m2_ck@d40ti,divider-clock}y @[acore_ckfixed-factor-clock}[&a&dpll1_fck@940ti,divider-clock}&y @['a'dpll1_ck@904ti,omap3-dpll-clock}'y  $ @ 4[adpll1_x2_ckfixed-factor-clock}[(a(dpll1_x2m2_ck@944ti,divider-clock}(y D[<a<cm_96m_fckfixed-factor-clock})[*a*omap_96m_fck@d40 ti,mux-clock}*y @[EaEdpll4_m3_ck@e40ti,divider-clock} y@[+a+dpll4_m3x2_mul_ckfixed-factor-clock}+[,a,dpll4_m3x2_ck@d00ti,gate-clock},y &[-a-omap_54m_fck@d40 ti,mux-clock}-.y @[8a8cm_96m_d2_fckfixed-factor-clock}*[/a/omap_48m_fck@d40 ti,mux-clock}/.y @[0a0omap_12m_fckfixed-factor-clock}0[GaGdpll4_m4_ck@e40ti,divider-clock} y@[1a1dpll4_m4x2_mul_ckti,fixed-factor-clock}1<JW[2a2dpll4_m4x2_ck@d00ti,gate-clock}2y &W[adpll4_m5_ck@f40ti,divider-clock}?y@[3a3dpll4_m5x2_mul_ckti,fixed-factor-clock}3<JW[4a4dpll4_m5x2_ck@d00ti,gate-clock}4y &W[jajdpll4_m6_ck@1140ti,divider-clock}?y@[5a5dpll4_m6x2_mul_ckfixed-factor-clock}5[6a6dpll4_m6x2_ck@d00ti,gate-clock}6y &[7a7emu_per_alwon_ckfixed-factor-clock}7[cacclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}&y p[9a9clkout2_src_mux_ck@d70ti,composite-mux-clock}&*8y p[:a:clkout2_src_ckti,composite-clock}9:[;a;sys_clkout2@d70ti,divider-clock};@y pjmpu_ckfixed-factor-clock}<[=a=arm_fck@924ti,divider-clock}=y $emu_mpu_alwon_ckfixed-factor-clock}=[dadl3_ick@a40ti,divider-clock}&y @[>a>l4_ick@a40ti,divider-clock}>y @[?a?rm_ick@c40ti,divider-clock}?y @gpt10_gate_fck@a00ti,composite-gate-clock} y [AaAgpt10_mux_fck@a40ti,composite-mux-clock}@y @[BaBgpt10_fckti,composite-clock}ABgpt11_gate_fck@a00ti,composite-gate-clock} y [CaCgpt11_mux_fck@a40ti,composite-mux-clock}@y @[DaDgpt11_fckti,composite-clock}CDcore_96m_fckfixed-factor-clock}E[ammchs2_fck@a00ti,wait-gate-clock}y [ammchs1_fck@a00ti,wait-gate-clock}y [ai2c3_fck@a00ti,wait-gate-clock}y [ai2c2_fck@a00ti,wait-gate-clock}y [ai2c1_fck@a00ti,wait-gate-clock}y [amcbsp5_gate_fck@a00ti,composite-gate-clock} y [amcbsp1_gate_fck@a00ti,composite-gate-clock} y [ a core_48m_fckfixed-factor-clock}0[FaFmcspi4_fck@a00ti,wait-gate-clock}Fy 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[amcbsp5_ick@a10ti,omap3-interface-clock}Jy  [amcbsp1_ick@a10ti,omap3-interface-clock}Jy  [aomapctrl_ick@a10ti,omap3-interface-clock}Jy [adss_tv_fck@e00ti,gate-clock}8y[adss_96m_fck@e00ti,gate-clock}Ey[adss2_alwon_fck@e00ti,gate-clock}y[adummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock}y [KaKgpt1_mux_fck@c40ti,composite-mux-clock}@y @[LaLgpt1_fckti,composite-clock}KLaes2_ick@a10ti,omap3-interface-clock}Jy [awkup_32k_fckfixed-factor-clock}@[MaMgpio1_dbck@c00ti,gate-clock}My [asha12_ick@a10ti,omap3-interface-clock}Jy [awdt2_fck@c00ti,wait-gate-clock}My [awdt2_ick@c10ti,omap3-interface-clock}Ny [awdt1_ick@c10ti,omap3-interface-clock}Ny [agpio1_ick@c10ti,omap3-interface-clock}Ny [aomap_32ksync_ick@c10ti,omap3-interface-clock}Ny [agpt12_ick@c10ti,omap3-interface-clock}Ny [agpt1_ick@c10ti,omap3-interface-clock}Ny [aper_96m_fckfixed-factor-clock})[ a per_48m_fckfixed-factor-clock}0[OaOuart3_fck@1000ti,wait-gate-clock}Oy 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y[^a^gpt9_mux_fck@1040ti,composite-mux-clock}@y@[_a_gpt9_fckti,composite-clock}^_per_32k_alwon_fckfixed-factor-clock}@[`a`gpio6_dbck@1000ti,gate-clock}`y[agpio5_dbck@1000ti,gate-clock}`y[agpio4_dbck@1000ti,gate-clock}`y[agpio3_dbck@1000ti,gate-clock}`y[agpio2_dbck@1000ti,gate-clock}`y [awdt3_fck@1000ti,wait-gate-clock}`y [aper_l4_ickfixed-factor-clock}?[aaagpio6_ick@1010ti,omap3-interface-clock}ay[agpio5_ick@1010ti,omap3-interface-clock}ay[agpio4_ick@1010ti,omap3-interface-clock}ay[agpio3_ick@1010ti,omap3-interface-clock}ay[agpio2_ick@1010ti,omap3-interface-clock}ay [awdt3_ick@1010ti,omap3-interface-clock}ay [auart3_ick@1010ti,omap3-interface-clock}ay [auart4_ick@1010ti,omap3-interface-clock}ay[agpt9_ick@1010ti,omap3-interface-clock}ay [agpt8_ick@1010ti,omap3-interface-clock}ay [agpt7_ick@1010ti,omap3-interface-clock}ay[agpt6_ick@1010ti,omap3-interface-clock}ay[agpt5_ick@1010ti,omap3-interface-clock}ay[agpt4_ick@1010ti,omap3-interface-clock}ay[agpt3_ick@1010ti,omap3-interface-clock}ay[agpt2_ick@1010ti,omap3-interface-clock}ay[amcbsp2_ick@1010ti,omap3-interface-clock}ay[amcbsp3_ick@1010ti,omap3-interface-clock}ay[amcbsp4_ick@1010ti,omap3-interface-clock}ay[amcbsp2_gate_fck@1000ti,composite-gate-clock}y[ a mcbsp3_gate_fck@1000ti,composite-gate-clock}y[amcbsp4_gate_fck@1000ti,composite-gate-clock}y[aemu_src_mux_ck@1140 ti,mux-clock}bcdy@[eaeemu_src_ckti,clkdm-gate-clock}e[fafpclk_fck@1140ti,divider-clock}fy@pclkx2_fck@1140ti,divider-clock}fy@atclk_fck@1140ti,divider-clock}fy@traceclk_src_fck@1140 ti,mux-clock}bcdy@[gagtraceclk_fck@1140ti,divider-clock}g y@secure_32k_fck fixed-clock[hahgpt12_fckfixed-factor-clock}hwdt1_fckfixed-factor-clock}hsecurity_l4_ick2fixed-factor-clock}?[iaiaes1_ick@a14ti,omap3-interface-clock}iy rng_ick@a14ti,omap3-interface-clock}iy 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tx0rx0tx1rx1!default/spidev@0spidevQlycspi@480ba000ti,omap2-mcspiyH 0+mcspi4CFGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-hsmmcyH Smmc1l=>txrxy!default/ mmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrx!default/mmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuyH mmu_isp[ammu@5d000000ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< commontxrx mcbsp1 txrx}fck disabledmcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?commontxrxsidetone mcbsp2mcbsp2_sidetone!"txrx}fckickokay[amcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZcommontxrxsidetone mcbsp3mcbsp3_sidetonetxrx}fckickokay!default/mcbsp@49026000ti,omap3-mcbspyI`mpu 67 commontxrx mcbsp4txrx}fck disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR commontxrx mcbsp5txrx}fck disabledsham@480c3000ti,omap3-shamshamyH 0d1Erx disabledsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreyH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivayH timer@48318000ti,omap3430-timeryH1%timer1timer@49032000ti,omap3430-timeryI &timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5+timer@4903a000ti,omap3430-timeryI*timer6+timer@4903c000ti,omap3430-timeryI+timer7+timer@4903e000ti,omap3430-timeryI,timer88+timer@49040000ti,omap3430-timeryI-timer98timer@48086000ti,omap3430-timeryH`.timer108timer@48088000ti,omap3430-timeryH/timer118timer@48304000ti,omap3430-timeryH0@_timer12Eusbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs+ Uehci-phyohci@48064400ti,ohci-omap3yHD Lehci@48064800 ti,ehci-omapyHH M`gpmc@6e000000ti,omap3430-gpmcgpmcynrxtxeq+0[anand@0,0ti,omap2-nand y sw$$$)08FUHfHw6+x-loader@0 X-Loaderybootloaders@80000U-Bootybootloaders_env@260000 U-Boot Envy&kernel@280000Kernely(@filesystem@680000 File Systemyhusb_otg_hs@480ab000ti,omap3-musbyH \]mcdma usb_otg_hs ` usb2-phy2dss@48050000 ti,omap3-dssyHok dss_core}fck+!default/dispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpoint[assi-controller@48058000 ti,omap3-ssissiokyHHsysgddGgdd_mpu+ }q ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHHtxrx CDssi-port@4805b000ti,omap3-ssi-portyHHtxrx EFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$+ *isp@480bc000 ti,omap3-ispyH H |ilports+bandgap@48002524yH%$ti,omap34xx-bandgapmemory@80000000mmemoryyhsusb2_power_regregulator-fixed phsusb2_vbus2Z2Z %*p[ahsusb2_phyusb-nop-xceiv ;G[asoundti,omap-twl4030 Romap3beagle[regulator-mmc2-sdio-poweronregulator-fixedpregulator-mmc2-sdio-poweron00 %d*'[adisplaysamsung,lte430wq-f0cpanel-dpilcd!default/ v portendpoint[apanel-timingT@* backlightgpio-backlight!default/    compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesstatusclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyspi-cphati,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplycd-gpiosbus-widthnon-removablecap-power-off-card#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-modephysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,wr-access-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsgpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspenable-active-lowenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-on